- Significant UVM SystemVerilog experience in complex test-benches
- Experience working with DRAM controller PHYs memory models is preferred
- Significant experience with general verification flows and metrics
- Excellent debug skills
- Working with big teams across multiple geographiesEXPERIENCE AND EDUCATION
- 7 or more years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;
- Strong Verilog/System Verilog knowledge
- Has developed or significantly changed components in UVM testbenches - monitors / checkers / sequences
- Some experience with SVA or formal are preferred.
- Ability to debug design/TB failures using logfiles and waveforms
- Knowledge of scripting language (PYTHON or PERL)
- Strong analytical skills and attention to detail;
- Strong written and communication skills
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Verification Engineer
2 weeks ago
ACL Digital Santa Clara, United StatesJob Description : We need someone familiar with UVM to run and debug tests. If they are capable, we will also ask them to write some testbench modules and components. Perhaps the most important thing is that they are diligentand good at communicating what they find and where the ...
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Verification Engineer
1 week ago
Broadcom Corporation San Jose, United StatesPlease Note: · 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: · Job duties include: Veri ...
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Verification Engineer
1 week ago
Broadcom Corporation San Jose, United StatesPlease Note: · 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: · The ASIC Product Divisio ...
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Verification Engineer
1 week ago
Broadcom Corporation San Jose, United StatesPlease Note: · 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: · The ASIC Product Divisio ...
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Verification Engineer
1 day ago
Broadcom Corporation San Jose, United StatesPlease Note: · 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: · The ASIC Product Divisio ...
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Verification Engineer
1 day ago
Broadcom Corporation San Jose, United StatesPlease Note: · 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: · Job duties include: Veri ...
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Verification Engineer
2 weeks ago
Synopsys Sunnyvale, United StatesOur Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world's broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabiliti ...
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Accelerator Verification Engineer
1 week ago
Ursus Inc Santa Clara, United StatesJOB TITLE: Accelerator Verification Engineer · LOCATION: (US) Santa Clara CA , Austin TX, Portland OR, Fort Collins CO · QUALIFICATIONS: · Join a cutting-edge hardware startup in Silicon Valley as a Silicon Verification Engineer. Our mission is to reimagine silicon and create ...
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Design Verification Engineer
1 week ago
Capgemini Engineering Santa Clara, United StatesJob Role: Design Verification Engineer · Location: Santa Clara, California · Job description: · We are seeking a Design Verification Engineer for our full-time role with Capgemini Engineering. · Key responsibilities: · General DV skills, someone who can understand the specs, work ...
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Design Verification Engineer
1 week ago
Mirafra Technologies Santa Clara, United StatesLooking to add DV Engineers in Irvine, San Diego and Santa Clara. · On going needs additional 10 engineers in team. · Position detail: SOC verification · Experience level : 5-20 years · Architect block and full-chip verification environments using HVLs and constrained random ...
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ASIC Verification Engineer
1 week ago
Penn Foster Inc Santa Clara, United StatesThe NVIDIA Clocks Team is looking for an ASIC Verification engineer to validate CPU, GPU and SOC clocks design. Our team is committed to delivering high-quality clocking and reset logic to various units in SOC and GPU ASIC. The complexity of the clocks and resets has increased ma ...
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Senior Verification Engineer
2 weeks ago
NVIDIA Santa Clara, United StatesWe are now looking for a Senior Verification Engineer for our Tegra groupNVIDIA is seeking outstanding Senior Verification Engineers to verify the design and implementation of the world's leading SoC's and GPU's. · The full job description covers all associated skills, previous ...
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Design Verification Engineer
1 week ago
Mirafra Technologies Santa Clara, United StatesLooking to add DV Engineers in Irvine, San Diego and Santa Clara. · Make sure to apply quickly in order to maximise your chances of being considered for an interview Read the complete job description below. · On going needs additional 10 engineers in team. · Position detail: S ...
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Senior Verification Engineer
1 week ago
NVIDIA Santa Clara, United StatesWe are now looking for a Senior Verification Engineer for our Tegra groupNVIDIA is seeking outstanding Senior Verification Engineers to verify the design and implementation of the worlds leading SoC's and GPU's. This position offers the opportunity to have real impact in a multi- ...
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Design Verification Engineer
1 week ago
Capgemini Engineering Santa Clara, United StatesWe are seeking a Design Verification Engineer with below skills. · Interested in this role You can find all the relevant information in the description below. · Total 10 years of experience in UVM based verification. · System Verilog assertions experience. · Familiarity with ...
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Design Verification Engineer
1 week ago
Capgemini Engineering Santa Clara, United StatesWe are seeking a Design Verification Engineer with below skills. · Total 10 years of experience in UVM based verification. · System Verilog assertions experience. · Familiarity with C/C++ model integration in verification environments. · Debug skills at IP and subsystem level ...
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Senior Verification Engineer
2 weeks ago
NVIDIA Santa Clara, United StatesWe are now looking for a Senior Verification Engineer for our Tegra group · NVIDIA is seeking outstanding Senior Verification Engineers to verify the design and implementation of the world's leading SoC's and GPU's. This position offers the opportunity to have real impact in a mu ...
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Senior Verification Engineer
1 week ago
NVIDIA Santa Clara, United StatesWe are now looking for a Senior Verification Engineer for our Tegra groupNVIDIA is seeking outstanding Senior Verification Engineers to verify the design and implementation of the worlds leading SoC's and GPU's. This position offers the opportunity to have real impact in a multi- ...
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Design Verification Engineer
2 weeks ago
Intel Santa Clara, United States**Job Description** · **Do Something Wonderful** · Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea ...
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Senior Verification Engineer
3 weeks ago
NVIDIA Santa Clara, United StatesSenior Verification Engineer - Displays page is loaded · Senior Verification Engineer - Displays · Apply · locations · US, CA, Santa Clara · time type · Full time · posted on · Posted Today · job requisition id · JR · We are looking for a Senior Verification Engineer t ...