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    Verification Engineer - Santa Clara, United States - ACL Digital

    ACL Digital
    ACL Digital Santa Clara, United States

    2 weeks ago

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    Description
    Job Description :
    • We need someone familiar with UVM to run and debug tests. If they are capable, we will also ask them to write some testbench modules and components. Perhaps the most important thing is that they are diligentand good at communicating what they find and where they are.
    • Develop test plans and test benches for module level verification
    • Run and debug failing regression tests. Report on the root cause. Write additional test cases to cover failures.
    • Work closely with hardware, software and systems engineering teams to develop models and test cases, to debug failing tests, and to validate operation and performance in simulation and at the system level
    • Develop test bench components such as UVM agents and behavioral models for simulation and emulation platforms
    • Develop Directed and random test cases
    • Run and monitor test regressions
    • Measure and report coverage
    JOB REQUIREMENTS
    • Experience with UVM
    • Solid knowledge of System Verilog and C/C++
    • Experience with Assertion based Verification
    • Experience with using random stimulus in conjunction with functional coverage
    • Working knowledge of scripting languages such as Python
    • Good communication skills
    PREFERRED
    • UVM Verification Environment development experience for module or full system level
    • Strong Object Oriented Programming ability
    • Familiarity with ARM, MIPS, Risc-V, ARC or other processors
    • Familiar with AMBA Buses (APB/AHB/AXI)
    • Knowledge or experience with Ethernet packet processing
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