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Verification Engineer
1 week ago
ACL Digital Santa Clara, United StatesJob Description : We need someone familiar with UVM to run and debug tests. If they are capable, we will also ask them to write some testbench modules and components. Perhaps the most important thing is that they are diligentand good at communicating what they find and where the ...
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Verification Engineer
6 days ago
Cynet Systems Inc Santa Clara CA, United States Full time, contractJob Role Verification EngineerJob Type Contract Job Location Santa Clara CA (or) Job DescriptionVerification Engineer for Memory Controller · • Significant UVM SystemVerilog experience in complex test-benches · • Experience working with DRAM controller PHYs memory models is prefe ...
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Verification Engineer
1 week ago
Broadcom Corporation San Jose, United StatesPlease Note: · 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: · The ASIC Product Divisio ...
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Verification Engineer
4 days ago
Broadcom Corporation San Jose, United StatesPlease Note: · 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: · The ASIC Product Divisio ...
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Verification Engineer
3 days ago
Broadcom Corporation San Jose, United StatesPlease Note: · 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: · Job duties include: Veri ...
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Verification Engineer
1 week ago
Synopsys Sunnyvale, United StatesOur Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world's broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabiliti ...
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Senior Verification Engineer
1 week ago
NVIDIA Santa Clara, United StatesWe are now looking for a Senior Verification Engineer for our Tegra groupNVIDIA is seeking outstanding Senior Verification Engineers to verify the design and implementation of the worlds leading SoC's and GPU's. This position offers the opportunity to have real impact in a multi- ...
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Design Verification Engineer
1 week ago
Mirafra Technologies Santa Clara, United StatesLooking to add DV Engineers in Irvine, San Diego and Santa Clara. · On going needs additional 10 engineers in team. · Position detail: SOC verification · Experience level : 5-20 years · Architect block and full-chip verification environments using HVLs and constrained random ...
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Senior Verification Engineer
6 days ago
SiFive Santa Clara, United StatesAbout SiFive · As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive's unrivaled compute platforms are co ...
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Design Verification Engineer
2 days ago
Capgemini Engineering Santa Clara, United StatesJob Role: Design Verification Engineer · Location: Santa Clara, California · Job description: · We are seeking a Design Verification Engineer for our full-time role with Capgemini Engineering. · Key responsibilities: · General DV skills, someone who can understand the specs, work ...
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Senior Verification Engineer
2 weeks ago
NVIDIA Santa Clara, United StatesSenior Verification Engineer - Displays page is loaded · Senior Verification Engineer - Displays · Apply · locations · US, CA, Santa Clara · time type · Full time · posted on · Posted Today · job requisition id · JR · We are looking for a Senior Verification Engineer t ...
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Senior Verification Engineer
2 weeks ago
NVIDIA Santa Clara, United StatesWe are now looking for a Senior Verification Engineer · NVIDIA is currently seeking a Verification Engineer with strong CPU, Memory subsystem, and Verification fundamentals to work in our CPU team. This position offers the opportunity to have real impact in a progressive, techno ...
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Systems Verification Engineer
1 day ago
J&J Family of Companies Santa Clara, United StatesSystems Verification Engineer W · Description · Description · Robotics & Digital Surgery, part of the Johnson & Johnson family of companies, is recruiting for a Systems Verification Engineer, located in Santa Clara, CA. · At Johnson & Johnson, we believe health is everything. Our ...
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Design Verification Engineers
1 week ago
Tachyum Santa Clara, United StatesWe are looking for talented Verification Engineers to expand our International Design Verification team. · Qualifications · Bachelor's or Master's in Electrical or Computer Science · 4 years of Design Verification experience · Very good understanding of Design Verification go ...
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Senior Verification Engineer
1 week ago
NVIDIA Santa Clara, United StatesWe are now looking for a Senior Verification Engineer for our Tegra groupNVIDIA is seeking outstanding Senior Verification Engineers to verify the design and implementation of the worlds leading SoC's and GPU's. This position offers the opportunity to have real impact in a multi- ...
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CPU Verification Engineer
6 days ago
Ampere Santa Clara, United StatesDesign Verification is an integral part of the chip design process that ensures our customers get the absolute highest quality products that meets their functional and performance requirements. · The DV team at Ampere Computing comprises of stellar folks who have dedicated thems ...
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Design Verification Engineer
3 days ago
Capgemini Engineering Santa Clara, United StatesWe are seeking a Design Verification Engineer with below skills. · Total 10 years of experience in UVM based verification. · System Verilog assertions experience. · Familiarity with C/C++ model integration in verification environments. · Debug skills at IP and subsystem level. · ...
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Senior Verification Engineer
1 week ago
NVIDIA Santa Clara, United StatesWe are now looking for a Senior Verification Engineer for our Tegra group · NVIDIA is seeking outstanding Senior Verification Engineers to verify the design and implementation of the world's leading SoC's and GPU's. This position offers the opportunity to have real impact in a mu ...
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Accelerator Verification Engineer
1 week ago
Ursus Inc Santa Clara, United StatesJOB TITLE: Accelerator Verification Engineer · LOCATION: (US) Santa Clara CA , Austin TX, Portland OR, Fort Collins CO · QUALIFICATIONS: · Join a cutting-edge hardware startup in Silicon Valley as a Silicon Verification Engineer. Our mission is to reimagine silicon and create ...
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Design Verification Engineer
2 weeks ago
Intel Santa Clara, United States**Job Description** · **Do Something Wonderful** · Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea ...
Design Verification Engineer - Santa Clara, United States - Mirafra Technologies
Description
Looking to add DV Engineers in Irvine, San Diego and Santa Clara.
Make sure to apply quickly in order to maximise your chances of being considered for an interview Read the complete job description below.
On going needs additional 10 engineers in team.
Position detail: SOC verification
Experience level : 5-20 years
Architect block and full-chip verification environments using HVLs and constrained random
techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA
○ Develop test plans and coverage metrics from specifications and write block and chip-level
tests in C,SV,UVM
○ Debug RTL and Gate simulations and work with design engineers to verify fixes.
○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.
○ Replicate silicon bugs in simulation environments and validate fixes or SW workarounds.
○ Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.
○ Evaluate latest verification methodologies and develop scripts etc. to automate verification
flows.