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Mahantesh Udikeri

Mahantesh Udikeri

Verification Engineer using SV UVM

Engineering / Architecture

Santa Clara, Santa Clara

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About Mahantesh Udikeri:

  • Around 20+ years of Industry experience involved in VLSI Functional Verification using with System Verilog UVM/VMM, Specman, Verilog.
  • Building pre-silicon verification environments from scratch for IP/SubSystem/SOC using the verification languages as Systemverilog (UVM and VMM based Methodology), Specman (i.e eRM based methodology), Verilog and c. Used the Constrained Random Verification and Coverage driven Verification Methodology.
  • Verilog, Verilog PLI, C and TCL based Verification.
  • Mixed Signal Verification and written a basic Verilog based Analog Models.
  • ATE Pattern Generation and support the ATE Engineers.
  • DDR3, AXI, SPI, JTAG, UART, I2C, AHB, APB, Super Hyway, PCI.
  • Building and Managing ASIC Verification Teams, interacting across multiple locations and groups. 

 

Experience

  • Around 20+ years of Industry experience involved in VLSI Functional Verification using with System Verilog UVM/VMM, Specman, Verilog.
  • Building pre-silicon verification environments from scratch for IP/SubSystem/SOC using the verification languages as Systemverilog (UVM and VMM based Methodology), Specman (i.e eRM based methodology), Verilog and c. Used the Constrained Random Verification and Coverage driven Verification Methodology.
  • Verilog, Verilog PLI, C and TCL based Verification.
  • Mixed Signal Verification and written a basic Verilog based Analog Models.
  • ATE Pattern Generation and support the ATE Engineers.
  • DDR3, AXI, SPI, JTAG, UART, I2C, AHB, APB, Super Hyway, PCI.
  • Building and Managing ASIC Verification Teams, interacting across multiple locations and groups. 

Helping in hiring the proper resources for the project, identifying the requirement and working with HR to interview and recruit new engineers.

Education

Bachelor of Engineering in Electrical and Electronics.

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