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    Design Verification Engineer - San Jose, CA, United States - XConn Technologies Holdings Inc.

    XConn Technologies Holdings Inc.
    XConn Technologies Holdings Inc. San Jose, CA, United States

    2 weeks ago

    Default job background
    Description

    Job Description:
    Provide design verification services for our SoC


    Responsibilities:
    Test bench development using System Verilog UVM
    Test plan and test case development with functional coverage, assertion, coverage property, coverage groups and coverage collections
    Regression setup and debug at RTL level and gate sim level working with design team


    Requirements:
    ~10+ Design Verification experience
    ~ Deep knowledge about System Verilog, UVM and verification coverage matrix
    ~ Familiar with Synopsys PCIe/CXL VIP and Mentor Graphics QVIP
    ~ Strong experience with PCIe/CXL protocol (PHY/DLLP/TLP)
    ~ Very familiar with the peripheral protocols such as UART, I2C, SPI Flash
    ~ Proficient in Perl scripting


    Job Type :
    Full-time


    Pay:
    $150, $200,000.00 per year


    Benefits:
    ~401(k)
    ~ Dental insurance
    ~ Health insurance
    ~ Life insurance
    ~ Paid time off
    ~ Vision insurance


    Schedule:
    ~8 hour shift
    ~ Monday to Friday


    Work Location:
    In person


    Employment Type:
    Full-time

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