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    Senior Design Verification Engineer - Los Angeles, United States - Cadence Design Systems

    Cadence Design Systems
    Cadence Design Systems Los Angeles, United States

    1 week ago

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    Description
    Cadence

    is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise.

    The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

    Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

    The Cadence Advantage

    The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.

    Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.

    The unique "One Cadence – One Team" culture promotes collaboration within and across teams to ensure customer success
    Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests

    You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.


    Job Summary:
    Drives development of products and technologies and has material responsibility for the success of that product/technology.

    VIP PE is expected to be an expert in DisplayPort domain of Verification IP family- protocol and product-wise.

    PE main role is to help accelerate VIP portfolio adoption at Cadence's top tier customers by supporting pre-sales technical activities.

    To ensure that, one must have strong verification expertise and understand customer design and verification flows.

    As a DP VIP and protocol expert, PE drives product knowledge transfer across our field engineers and customer, providing training and developing collaterals.

    The PE will also need to translate high-level requirements from customers into a technical spec and drive the product definition that fits the customer needs.

    PE is expected to work independently and collaborate with other team members ( RnD, Marketing, support) to ensure all dimensions of the product are aligned.

    This role requires approximately 20% travel on average.


    Job responsibilities:
    Leads projects with high resource, risk and/or complexity
    Develops and leads large and multiple cross-functional and cross-organizational programs, initiatives, and activities with high resource requirements, risk and/or complexity
    Continually evaluates technology effectiveness/data interoperability of complex systems
    Manages issue resolution with vendors on tech/product quality and functionality and influences vendor roadmap and direction of products

    Communicates highly-complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view.


    Experience and Technical Skills required:
    Bachelors or masters degree in electrical, Electronics & Comm Engineering
    At least 8-10 years of experience with Functional Verification and Design
    Working knowledge with any of the DisplayPort protocol is a must
    Experience with Developing Verification environments using System Verilog
    Working knowledge and experience with the UVM methodology
    Good experience on solving complex problems where analysis of situations or data requires an in-depth evaluation of various factors.
    Exercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results.
    Excellent problem-solving and debugging skills

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