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Verification Engineer - Azusa, United States - Sun Technologies
Description
All-In-One Scriptless Test Automation SolutionLocation
,
California
Duration
: 6 Months contract with possible extension
Job Description
Work Location:
Azusa, CA (Would like the candidate to spend first 1-2 weeks on-site for tool set-up / meeting the team; the rest of the job can be done remotely.)
Pay Range:
$60/hr-$75/hr; the pay rate may differ depending on your skills, education, experience, and other qualifications.
Featured Benefits:
Medical insurance in compliance with the ACA
401(k).
Sick leave in compliance with applicable state, federal, and local laws
Required:
Minimum of 5 years of writing SystemVerilog and UVM as a primary job function
Experience with verification of designs written in VHDL
Experience with Linux command-line workflows
Experience writing TCL to control verification tools
Demonstrated ability in root-cause analysis of test failures
Experience working closely with RTL designers to collaboratively resolve verification test failures
Experience with Git SCM using LFS and Submodules
10 years of writing SystemVerilog and UVM as a primary job function
Experience creating prediction models from functional requirements documentation using SystemVerilog or SystemC
Experience with DPI-based simulator interaction for stimulus and prediction
Proficiency in scripting in either Perl or Python for parsing and manipulating text files
Experience with Questa Sim and Visualizer
Experience with the UVM-Framework workflow
Experience writing split Class/xRTL BFMs for use with both simulation and Co-Emulation (Veloce experience preferred)
Experience writing and maintaining Verification Plan Documents
Experience working on USG Contracts and the associated documentation/process expectations
Experience with common interface specifications used in spacecraft
Experience verifying designs targeting radiation-hardened Virtex FPGAs
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