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    Senior Staff Digital Verification Engineer - Los Angeles, United States - Alpha & Omega Semiconductor

    Alpha & Omega Semiconductor
    Alpha & Omega Semiconductor Los Angeles, United States

    Found in: Lensa US 4 C2 - 1 week ago

    Default job background
    Description


    At Alpha and Omega Semiconductor (AOS), we design, develop and globally supply a broad range of power semiconductors, including a wide portfolio of Power MOSFET, IGBT, IPM, TVS, GaN/SiC, Power IC and Digital Power products.

    You will find our products in everyday applications including personal computers, graphic cards, gaming consoles, TVs, home appliances, smart phones, power tools, and more At the center of our innovation is our people who bring passion, talent, and a collaborative atmosphere to our growing company.

    We offer an impressive benefit package and career development opportunities. If you are ready to take the next step in your career working with a team of passionate and talented people, then take a look at the job opportunity below to POWER your career


    Overall Purpose of Position:


    The engineer will work closely with the design team, and be responsible for all aspects of verifying that the digital core is fully functionally compliant with the specification at the top level.

    They will be responsible for the verification environment and be able to develop models for analog.


    Primary Job Responsibilities:
    Managing the digital verification environment for the design
    Setting methodologies and guidelines for digital verification on the project
    Reviewing the internal/customer specification and generating a full test plan and environment to confirm compliance
    Reviewing RTL to debug and understand any issues, and propose solutions
    Working closely with the design team to resolve any issues
    Design of some digital sub-blocks


    Qualifications:
    BSEE +5 years or MSEE +3 years of relevant experience. At least 3 years of digital verification, including test writing and verification of several products
    Experience with using the Cadence Virtuoso software and AMS simulation environment
    Comfortable with exploring the analog schematic hierarchy in Cadence
    Able to write and debug System Verilog models. Previous real number modelling experience a plus
    Can create thorough block and system level SV assertions
    Experience in debugging simulation issues and bug identification
    A good understanding of UVM, and the ability to import an environment from an existing project and improve upon it
    Strong scripting skills is a highly desirable (csh, Python and TCL)
    Able to work well in a remote team environment, including good communication and inter-personal skills
    Self-starter able to manage his/her own time effectively

    *This position is eligible for paid time off and to participate in an annual bonus program

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