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- Create UVM simulation plan from design specification.
- Create or modify UVC, Score Board, Monitor, and test cases.
- Verify until functional coverage and code coverage meet project threshold.
- Document results.
- 5+ years of experience in ASIC/FPGA Design Verification
- 1-2 years of UVM tool
- Cadence Xcelium verification tool
Design Verification Engineer - El Segundo, United States - Kronos Consulting LLC
Description
Responsibilities:
Please make an application promptly if you are a good match for this role due to high levels of interest.Required Skills: