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Engineer - Azusa, United States - PDS Tech Commercial, Inc.
Description
PDS Tech Commercial, Inc. is seeking candidates for an Engineer Digital 3 in Palmdale, CA. If you have experiencewriting System Verilog and UVM, this is the opportunity you should apply for
Job Title:
Engineer Digital 3Job Type:
Full time; 6 month contractSchedule:
9x80Location:
Azusa, CAPay Rate:
$71 per hour
Job SummaryThe candidate will be responsible for writing System Verilog and UVM as part of their primary role in the verification of hardware designs written in VHDL.
They will work within a Linux environment using TCL scripts to control verification tools and collaborate with RTL designers to resolve test failures.
Even Simpler:
The job is for someone who writes special computer code to make sure that other computer codes for hardware work correctly without any problems.
Basic RequirementsBachelor's degree requiredMinimum of 5yrs writing System Verilog and UVM as a primary job functionExperience with verification of designs written in VHDLExperience with Linux command line workflowsExperience writing TCL to control verification toolsDemonstrated ability in root-cause analysis of test failuresExperience working closely with RTL designers to collaboratively resolve verification test failuresExperience with Git SCM using LFS and SubmodulesDesired Requirements~10yrs writing System Verilog and UVM as a primary job function~ Experience creating prediction models from functional requirements documentation using System Verilog or SystemC~ Experience with DPI based simulator interaction for stimulus and prediction~ Proficiency scripting in either Perl or Python for parsing and manipulating text files~ Experience with Questa Sim and Visualizer~ Experience with the UVM-Framework workflow~ Experience writing split Class/xRTL BFMs for use with both simulation and Co-Emulation (Veloce experience preferred)~ Experience writing and maintaining Verification Plan Documents~ Experience working on USG Contracts and the associated documentation/process expectations~ Experience with common interface specifications used in spacecraft~ Experience verifying designs targeting radiation hardened Virtex FPGAs
Pay Details:
$71.00 per hourBenefit offerings available for our associates include medical, dental, vision, life insurance, short-term disability, additional voluntary benefits, EAP program, commuter benefits and a 401K plan. Our benefit offerings provide employees the flexibility to choose the type of coverage that meets their individual needs. In addition, our associates may be eligible for paid leave including Paid Sick Leave or any other paid leave required by Federal, State, or local law, as well as Holiday pay where applicable.
Equal Opportunity Employer/Veterans/DisabledTo read our Candidate Privacy Information Statement, which explains how we will use your information, please navigate to/
The Company will consider qualified applicants with arrest and conviction records subject to federal contractor requirements and/or security clearance requirements.
