- Testbench development - System Verilog UVM and C tests
- Integration/development of C tests/APIs and SW build flow
- Integration/development of UVM mailboxes and HW/SW communication components
- Test plan development
- Power Aware testbench development and simulations
- Seamless porting between simulation/emulation/prototyping platforms
- Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
- Coverage collection and closure
- Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
- Engage with the team to drive continuous improvement to the verification environment to find more bugs and improve coverage
- Work as a team to grow together.
- Mentor and coach junior team members
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Verification Engineer
3 days ago
Broadcom Corporation San Jose, United StatesPlease Note: · 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: · The ASIC Product Divisio ...
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Verification Engineer
2 days ago
Broadcom Corporation San Jose, United StatesPlease Note: · 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: · Job duties include: Veri ...
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Verification Engineer
1 week ago
Broadcom Corporation San Jose, United StatesPlease Note: · 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: · The ASIC Product Divisio ...
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Verification Engineer
1 week ago
ACL Digital Santa Clara, United StatesJob Description : We need someone familiar with UVM to run and debug tests. If they are capable, we will also ask them to write some testbench modules and components. Perhaps the most important thing is that they are diligentand good at communicating what they find and where the ...
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Verification Engineer
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Cynet Systems Inc Santa Clara CA, United States Full time, contractJob Role Verification EngineerJob Type Contract Job Location Santa Clara CA (or) Job DescriptionVerification Engineer for Memory Controller · • Significant UVM SystemVerilog experience in complex test-benches · • Experience working with DRAM controller PHYs memory models is prefe ...
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Design Verification Engineer
4 days ago
Theery San Jose, United StatesCompany Description: We are a cutting-edge technology company specializing in the development of advanced ASIC designs for various applications. Our team is composed of innovative individuals dedicated to pushing the boundaries of what's possible in the semiconductor industry. We ...
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Design Verification Engineer
1 week ago
Intelliswift Software Inc San Jose, United StatesDesign Verification Engineer - Remote / San Jose, CA · Duration 6 months + (can be extended longer) · San Jose, CA / Remote · Design Verification Engineer · UVM · System Verilog · Test Bench Development · SystemC (preferred) · strong C/C++ · ...
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ASIC Verification Engineer
1 week ago
European Recruitment San Jose, United StatesASIC Verification Engineer- System Verilog / UVM /RTL logic Design · We are partnered up with a well-established Semiconductor organisation who enable state of the art perception for autonomous vehicles who are looking for Senior ASIC Verification Engineer to join their team in ...
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Design Verification Engineer
6 days ago
Acceler8 Talent San Jose, United StatesDesign Verification Engineer – San Jose, CA · Acceler8 Talent is currently seeking a skilled Design Verification Engineer to join one of the world's leader in AI innovation, that specializes in the design of high-performance, low-power AI inference solutions. · You'll play a key ...
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Design Verification Engineer
1 week ago
Synapse Design San Jose, United StatesSynapse Design is looking forward to hire Design Verification Engineer expert. · Experience:: +10 years · Requirements: · Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, Perl/Python. · Proficient in debugging complex SOC or CPU core designs involvin ...
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Design Verification Engineer
1 week ago
Verilab San Jose, United StatesJob Summary · We invite you to join our highly motivated team of consultants, providing clients with the very best in verification. You will be exposed to a diverse range of designs and application areas. We work on leading edge Audio, Automotive, Comms, Processors, Space, Video ...
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IC Verification Engineer
3 days ago
Broadcom Corporation San Jose, United StatesPlease Note: · 1. If you are a first time user, please create your candidatelogin account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: Job duties include: · Archi ...
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Formal Verification Engineer
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LeadStack Inc. San Jose, United StatesLeadStack Inc. is an award-winning, one of the nation's fastest-growing, certified minority-owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to par ...
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ASIC Verification Engineer
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ASIC Verification Engineer
4 days ago
European Recruitment San Jose, United StatesASIC Verification Engineer- System Verilog / UVM /RTL logic Design · We are partnered up with a well-established Semiconductor organisation who enable state of the art perception for autonomous vehicles who are looking for Senior ASIC Verification Engineer to join their team in C ...
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IC Verification Engineer
1 week ago
Broadcom Corporation San Jose, United StatesPlease Note: · 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: · Job duties include: · • ...
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Principal Verification Engineer
1 week ago
Rambus San Jose, United StatesOverview: · Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional?Principal Verification Engineer?to join our Memory Interconnect Design team in San Jose, California. Candidates will be joining some of the brightest inventors and engineers in the worl ...
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Design Verification Engineer
1 week ago
Energy Jobline CVL San Jose, CA, United StatesGreetings from LeadStack Hope you are doing well and staying safe We have an immediate contract position with our direct client. · If you are interested and available, please respond with your resume ASAP and suggest the best time when I can call you. Job Details: LeadStack Inc. ...
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Design Verification Engineer
4 days ago
Verilab San Jose, United StatesJob Summary · We invite you to join our highly motivated team of consultants, providing clients with the very best in verification. You will be exposed to a diverse range of designs and application areas. We work on leading edge Audio, Automotive, Comms, Processors, Space, Video ...
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Principal Verification Engineer
1 week ago
Broadcom Corporation San Jose, United StatesPlease Note: · 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) · 2. If you already have a Candidate Account, please Sign-In before you apply. · Job Description: · You will be joining Broa ...
Design Verification Engineer - San Jose, United States - Intelliswift Software
Description
Title: Design Verification Engineer
Location: San Jose, CA, Austin, TX, Phoenix, AZ
Duration: 12 Months.
Pay Rate: $75 to $80/hr
Job Description:
Here's what you need:
· A minimum of three years of experience with SoC Design Verification
· Bachelor's Degree or equivalent (12 years) work experience (If an, Associate's Degree with 6 years of work experience)
Skills: CPU, Cortex/ARM Cortex, UVM, Verilog, Test Bench
Intelliswift Software is an Equal Employment Opportunity (EEO) employer and does not discriminate on the basis of age, color, national origin, citizenship status, physical or mental disability, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, genetic information, marital status, status with regard to public assistance, veteran status or any other characteristic protected by federal, state or local law.