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    Design Verification Engineer - San Jose, CA, United States - Energy Jobline CVL

    Energy Jobline CVL
    Energy Jobline CVL San Jose, CA, United States

    4 weeks ago

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    Description

    Greetings from LeadStack Hope you are doing well and staying safe We have an immediate contract position with our direct client.

    If you are interested and available, please respond with your resume ASAP and suggest the best time when I can call you


    Job Details:
    LeadStack Inc. is an award-winning, one of the nation's fastest-growing, certified minority-owned (MBE) staffing services provider of contingent workforce.

    As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world.


    Title :
    Design & Verification Engineer (GPU)

    Location :
    San Jose, CA - Hybrid (3 days onsite)

    Duration : 12 months contract Rate: Market rate/DoE

    Must Have:

    • Knowledge of Block-level (unit level)
    • Debugging and development
    • UVM, SystemVerilog exp
    • 8 to 10 years of hands-on related exp As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date IEEE UVM version will place you among the elite within our profession.

    Requirements Role and Responsibilities:

    Key responsibilities include:
    Work with architects and designers to build verification environments and test plans. Craft functional verification coverage strategy to ensure complete test suite implementation. Develop assertions and checks to optimize isolation time and produce meaningful failing signatures. Analyze failing tests to root cause along, working with RTL and reference modeling teams. Provide input on Architectural and Micro-Architectural specifications for testability and accuracy. Examine code coverage results, identifying exclusions and improving stimulus.

    Take ownership of key milestone closure by meeting phase gate pass rates, coverage quality, and other quality metrics Skills and Qualifications:

    Minimum requirements:

    BS in Computer Engineering, BSEE or comparable and 5+ years of industry experience in a design verification role Proficient in System Verilog/UVM/OVM, and OOP/C++ Deep understanding of constrained randomization and the development of efficient test suites Experience with code coverage and functional coverage-driven verification methodology.

    Experience in creating, running, and debugging of SystemVerilog/UVM constraint-random testbench.

    Working knowledge of scripting such as Python or Perl Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines qualifications: MS CE/EE with 5+ years of industry experience in verification Good verbal and written communication skills Experience of GPU or CPU is a plus.

    If you are interested, please share your updated resume and the best time and number to connect over the phone.

    In case you are not available/interested, will appreciate if you can share it with your friends/network.

    Your referrals are appreciatedI can be reached on or (phone number removed)Take care and I hope you have a great dayBest Regards, Santosh Singh Senior Technical Recruiter C.

    (phone number removed)A. 611 Gateway Blvd, Ste 120South San Francisco, CA 94080W. #J-18808-Ljbffr
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