Kun liu

I am currently looking for a Digital design/ ASIC/ SoC engineer position.

Have deep knowledge of microprocessor architecture including pipeline, branch prediction, Out-of-Order execution, cache coherence

Scripting skills: Python, C language, Verilog, SystemVerilog

Familiar with clock domain crossing (CDC), Static Timing Analysis (STA). 

Validation: Deeply understand DFT, MBIT, BIST, JTAG/Boundary Scan, ATPG

RSA Cryptography SystemRSA Cryptography System

Sep 2019 - Nov 2019Sep 2019 - Nov 2019

•Designed a full custom transistor-level schematics and layout for the decryption part of the system which consists of Modified (radix-4) Booth Multiplier, Barrett Reduction algorithm based modulo, and Montgomery Modular Exponential unit.
•Degbugged RSA layout for LVS and DRC match.
•Simulations, layout, and design work was accomplished using Cadence Virtuoso in a Linux Environment.
•Developed a Python script to generated 5 test cases and its corresponding result used to verify the functionality of the schematic

I received my Master's degree in Electrical Engineering from University of Southern California.