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ASIC/FPGA Design Engineers - New York, United States - P. Chappel Associates Inc
Description
Our client is a dynamic growing company who have developed a revolutionary new computer architecture that is massively parallel, provides unprecedented scalability and will open a new frontier in software development.
Several systems have been installed and we are searching for a few key players to join the team in the development of a cutting-edge new product.
New architecture will target data analysis, cyber security, machine learning/AI, training, etc. Qualified candidates will be talented team players who want to play a key role in this ever changing environment. Experience with FPGA, ASIC and System Verilog is required. Small and/or startup company experience is greatly desired as is full product development lifecycle. HPC experience would be a plus.Competitive base salary ($100-125K for junior; $180-220K for senior/principal) plus generous stock options.
We are also recruiting for FPGA/ASIC Verification Engineers and Software Engineers for the same great company.
ASIC/FPGA Design Engineers – 2 open positions: one senior to principal level which is
remote
and 1 junior to intermediate level will have a hybrid work model in New York.
ASIC Design Engineers will design and implement IP used in FPGA or ASIC for this revolutionary new computer architecture. This is an outstanding opportunity for ASIC Design Engineers to work in a dynamic environment with renowned experts.
At present Intel FPGAs are being used.
Duties include:
logic design using Verilog / System Verilog, FPGA implementation and testing.
Qualifications include:
BSEE or MSEE, 2-5 years of relevantexperience for junior to mid-level; more experience for senior to principal level
Experience writing Verilog, TCL or other scripting language experience
Programming in C or similar languages, understanding ofcomputer architecture
Track record of getting things done and solving problems
Experience working in a small, dynamic environment.
I'm interested
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