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    Design Verification Engineer, Silicon Engineering - Sunnyvale, United States - META

    META
    META Sunnyvale, United States

    2 weeks ago

    Meta background
    Description

    Meta's Reality Labs(RL) focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta RL Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP implementations and contribute to development and optimization of state of the art vision and sensing algorithms. You will work closely with researchers, architects and designers in creating test bench requirements and test cases for multiple state of the art IPs. Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today-beyond the constraints of screens, the limits of distance, and even the rules of physics.

    Design Verification Engineer, Silicon Engineering (University Grad) Responsibilities

    • Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification.
    • Drive design verification to closure based on defined verification metrics on test plan, functional and code coverage.
    • Debug, root cause and resolve functional failures in the design, partnering with the design team.
    • Collaborate with cross functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring highest design quality.
    Minimum Qualifications
    • Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
    • Knowledge of System Verilog, VHDL or similar hardware description language.
    • Knowledge of Computer Architecture, Logic Design fundamentals, object oriented programming concepts.
    • Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment.
    Preferred Qualifications
    • Currently has, or is in the process of obtaining, a Master's degree in Electrical Engineering, Computer Engineering, Computer Science or similar technical field.
    • Creativity and problem solving skills.
    • Scripting capability with Python or Perl.
    • Knowledge in object oriented programming/UVM based verification environments.
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