-
Verification Engineer
2 days ago
Collabera Sunnyvale, United States· Home · Search Jobs · Job Description · Verification Engineer · Contract: Sunnyvale, California, US · Salary: $50.00 Per Hour · Job Code: · End Date: · Days Left: 27 days, 3 hours left · Apply · Job Summary: · Working under limited supervision, performs moderate risk/mo ...
-
DfT Verification Engineer
1 day ago
Oho Group Ltd Mountain View, United StatesA RISC-V start up is looking for a DFT Verification Engineer who wants to accelerate their career within a hugely accelerating business · My client is circa 400 people worldwide and has lured some of the top engineers from Apple & some of the household named Semi-Conductors. · ...
-
Design Verification Engineer
3 weeks ago
Acceler8 Talent Mountain View, United StatesAcceler8 Talent has recently partnered with a company that is redefining AI hardware, focusing on maximizing performance for large language models (LLMs) like GPT. With a commitment to cost efficiency and optimizing performance-per-dollar, their technology offers competitive late ...
-
Hardware Verification Engineer
1 week ago
BrickRed Systems Mountain View, United StatesWe are seeking an experienced and highly skilled Silicon Verification Engineer to join our dynamic team. The ideal candidate will have a robust background in ASIC design and verification, with a strong proficiency in SystemVerilog and UVM methodologies. You will be responsible fo ...
-
Software Verification Engineer
1 week ago
Rangam Sunnyvale, United StatesJob requirements: · Bachelor's degree in software engineering, computer science, or a related engineering field with 2+ years working experience. · Working from requirement specifications to develop, maintain, and update test procedures and test scripts. · Develop automation veri ...
-
design verification Engineer
1 week ago
Diverse Lynx Mountain View, United StatesPosition: design verification Engineer · Location: Mountain view, CA · Job Type: Fulltime/contract · Requirement For Performance DV · DV engineer with 5- 8 years of experience. · Traditional DV (SV/UVM )as well as performance DV. · For performance DV, experience with Python sc ...
-
Design Verification Engineer
1 week ago
Understanding Recruitment Mountain View, United StatesAcceler8 Talent has recently partnered with a company that is redefining AI hardware, focusing on maximizing performance for large language models (LLMs) like GPT. With a commitment to cost efficiency and optimizing performance-per-dollar, their technology offers competitive late ...
-
silicon verification engineer
2 weeks ago
Randstad Mountain View, United Statessilicon verification engineer. · mountain view , california · posted 1 day ago · job details · summary · $ $72.72 per hour · contract · bachelor degree · category computer and mathematical occupations · reference · job details · job summary: · Define, document, and impleme ...
-
Silicon Verification Engineer
3 weeks ago
BrickRed Systems Mountain View, United StatesWe are seeking a highly skilled Silicon Verification Engineer to join our team. The ideal candidate will be responsible for writing Silicon verification tests, running and debugging tests, and ensuring the overall quality and functionality of our silicon designs. This role requir ...
-
design verification Engineer
1 day ago
Diverse Lynx Mountain View, United StatesPosition: design verification Engineer · Location: Mountain view, CA · Job Type: Fulltime/contract · Requirement For Performance DV DV engineer with 5- 8 years of experience. · Traditional DV (SV/UVM )as well as performance DV. · For performance DV, experience with Python ...
-
Verification Engineer
19 hours ago
Syncreon Consulting Palo Alto, United StatesJob Description · Job DescriptionCompany Description · We work as trusted business partners and always strive to deliver the most value and highest return on investment for our clients. We are highly trained business professionals with strong understanding of clients need. We wor ...
-
CPU Design Verification Engineer
1 day ago
Prodapt ASIC services (Formerly Innovative Logic) Mountain View, United StatesProdapt ASIC services (formerly Innovative Logic) is the leading provider of SoC ASIC/FPGA and Embedded Software services. Our business model is to offer our services based on turnkey, Offshore design center (ODC) or staff augmentation. · We're seeking a CPU Design Verification ...
-
Design Verification Engineer
1 week ago
Quest Global Sunnyvale, United StatesHello , · Hope you doing good · Job Profile description. · location - Sunnyvale, California, United States · 7+ YOE in DV. · IP verification experience using SV/UVM methodology. · Excellent coding and debugging skills, should have exp. In coding various TB components. · AMBA pro ...
-
Senior Design Verification Engineer
1 day ago
Oho Group Ltd Mountain View, United StatesA $100m+ VC backed RISC-V scale up are looking for multiple Verification Engineers as they continue to accelerate their growth this year · They are at 400 people worldwide so have already been able to circumnavigate a lot of the typical speedbumps that effect early stage companie ...
-
Design Verification Engineer
1 day ago
Protingent Sunnyvale, United StatesProtingent Staffing has an exciting contract opportunity for Design Verification Engineer with our client located in Sunnyvale, CA. Job Responsibilities: - Responsibilities includes starting from test planning to closing verification using coverage m Verification, Engineer, Desig ...
-
Design Verification Engineers
1 day ago
Tachyum Sunnyvale, United StatesWe are looking for talented Verification Engineers to expand our International Design Verification team. · Qualifications · Bachelor's or Master's in Electrical or Computer Science · 4 years of Design Verification experience · Very good understanding of Design Verification go ...
-
Design Verification Engineer
1 day ago
NR Consulting Sunnyvale, United StatesJob Title: Design Verification Engineer · Duration: 12 mos + Possible extension · Location: : Sunnyvale CA · Description: · •Strong DV background (test plan development, test writing, SystemVerilog, UVM) · Duties:Write and augment existing testplans. · Implement testbench and s ...
-
Design Verification Engineer
4 days ago
Cynet Systems Inc. Sunnyvale, United StatesSkills, Experience, Education and Training: · Advanced knowledge of HVL methodology (UVM). · Expertise in HVL and HDL (System Verilog, Verilog). · Experience defining coverage space and writing coverage model. · Experience with System Verilog Assertion (SVA) is a plus. · Team pl ...
-
Senior Verification engineer
2 days ago
TWO95 International Sunnyvale, United StatesHi, · Title: Lead / Senior Verification engineer · Location: San Jose, CA / Santa Clara, CA · Duration: 6+ Months · Rate: $Open Skills: UVM and System Verilog Requirement:. · • 5+ or more years of proven experience on ASIC / SoC / IP Verification. · • Strong experience in S ...
-
Software Verification Engineer
5 days ago
Ampcus Incorporated Palo Alto, United States ContractSoftware Verification Engineer Palo Alto CA. (Onsite - Hybrid - 3 days from Office) 6+ Months · Job Description: · We are seeking an exceptionally skilled software testing lead with solid experience leading verification testing in a regulated environment preferably for IVD- ...
Silicon Verification Engineer - Mountain View, United States - Ursus Inc
Description
JOB TITLE:
Silicon Verification Engineer
LOCATION:
Santa Clara CA , Austin TX, Portland OR, Fort Collins
CO
SALARY:
K annual
Responsibilities
Work closely with architecture and RTL designers on verifying the functionality correctness of the design
Reviewing Architecture and Design Specifications
Develop test plans and test environments
Develop tests in assembly, C/C++, SystemVerilog, or vectors according to test plans
Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered
Develop checkers in SystemVerilog or C-base transactors to verify the design
Write assertions and apply formal verification to the designImplementing test benches, generating directed/constrained random tests
Debugging failures, running simulations, tracking bugs
Handling schedules and supporting multi-functional engineering effortAssisting in verification flows, automation scripts and regressions
Requirements
In-depth knowledge of digital logic design, CPU/SOC architecture and microarchitecture.
Sophisticated knowledge of SystemVerilog.
Experienced level knowledge C/C++.Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection.
Basic knowledge of formal verification methodology is a plus.Excellent knowledge of one of the scripting languages such as Python, TCL is a plus.
Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Ability to work well in a team and be productive under aggressive schedules.
Education and Experience
PhD, Master's Degree or Bachelor's Degree in technical subject area.
IND123
#J-18808-Ljbffr