- 5+ or more years of proven experience on ASIC / SoC / IP Verification.
- Strong experience in SystemVerilog and UVM verification methodologies
- Proficiency in Object Oriented programming, computer architecture and data structures
- Strong analytical/problem solving skills and pronounced attention to details
- Strong interpersonal and communication skills
- Must be comfortable working across geographiesNote: If interested please send your updated resume and include your rate requirement along with your contact details with a suitable time when we can reach you. If you know of anyone in your sphere of contacts, who would be a perfect match for this job then, we would appreciate if you can forward this posting to them with a copy to us.
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Tachyum Sunnyvale, United StatesWe are looking for talented Verification Engineers to expand our International Design Verification team. · Qualifications · Bachelor's or Master's in Electrical or Computer Science · 4 years of Design Verification experience · Very good understanding of Design Verification go ...
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Amick Brown Sunnyvale, United StatesJob Description · Job DescriptionAmick Brown is seeking an experienced Design Verification Engineer for our direct client. · Location: Sunnyvale, CA · Duration: 6 Months · Estimated pay range: $ per client contract and candidate skills, experience and work location. · Job Descri ...
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META Sunnyvale, United StatesMeta's Reality Labs(RL) focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta RL Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine lear ...
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Protingent Sunnyvale, United StatesProtingent Staffing has an exciting contract opportunity for Design Verification Engineer with our client located in Sunnyvale, CA. Job Responsibilities: - Responsibilities includes starting from test planning to closing verification using coverage m Verification, Engineer, Desig ...
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Formal Verification Engineer
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NR Consulting Sunnyvale, United StatesJob Title :- Formal Verification Engineer · Job Location :- Sunnyvale, CA · Position Type:- Contract · Education & Experience Required: · •Knowledge of Formal verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, · connectivity etc · •5+ ...
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Design Verification Engineer
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Amick Brown Sunnyvale, United StatesJob Description · Job Description · Amick Brown is seeking an experienced · Design Verification Engineer · for our direct client. · Location : · Sunnyvale, CA · Duration: · 6 Months · Estimated pay range: · $ per client contract and candidate skills, experience and work lo ...
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Design Verification Engineer
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NR Consulting Sunnyvale, United StatesJob Title: Design Verification Engineer · Duration: 12 mos + Possible extension · Location: : Sunnyvale CA · Description: · •Strong DV background (test plan development, test writing, SystemVerilog, UVM) · Duties:Write and augment existing testplans. · Implement testbench and s ...
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Design Verification Engineer
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Cynet Systems Inc. Sunnyvale, United StatesSkills, Experience, Education and Training: · Advanced knowledge of HVL methodology (UVM). · Expertise in HVL and HDL (System Verilog, Verilog). · Experience defining coverage space and writing coverage model. · Experience with System Verilog Assertion (SVA) is a plus. · Team pl ...
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Verification Engineer
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Collabera Sunnyvale, United StatesHome · Search Jobs · Job Description · Verification Engineer · Contract: Sunnyvale, California, US · Salary: $50.00 Per Hour · Job Code: · End Date: · Days Left: 27 days, 3 hours left · Apply · Job Summary:Working under limited supervision, performs moderate risk/moderat ...
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Design Verification Engineer
1 hour ago
QuEST Global Sunnyvale, United StatesHello , · Hope you doing good · Job Profile description. · location - Sunnyvale, California, United States · 7+ YOE in DV. · IP verification experience using SV/UVM methodology. · Excellent coding and debugging skills, should have exp. In coding various TB components. · AMBA pr ...
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Design Verification Engineer
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Mirafra Technologies Santa Clara, United StatesLooking to add DV Engineers in Irvine, San Diego and Santa Clara. · On going needs additional 10 engineers in team. · Position detail: SOC verification · Experience level : 5-20 years · Architect block and full-chip verification environments using HVLs and constrained random ...
Senior Verification engineer - Sunnyvale, United States - TWO95 International
Description
Hi,Title:
Lead / Senior Verification engineer
Location:
San Jose, CA / Santa Clara, CA
Duration: 6+ Months
Rate:
$
Open Skills:
UVM and
System Verilog Requirement:
Ajith Kumar |Sourcing Expert
TWO95 International Inc,
phone number removed) Ext 1244* (url removed)
(url removed)(phone number removed)/
(url removed)
1101, N Kings Hwy, Suite #200 Cherry Hill ,NJ
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