- Exercise EDA tools to evaluate and measure quality, performance, and design targets of standard cells.
- Develop, maintain, and validate automation and methodologies for improved standard cell collateral quality.
- Maintain validation tool configurations, educate stakeholders on validation tool capabilities, and support stakeholders for results review.
- Possesses written and verbal communication skills
- Customer/result orientation and the ability to work with external, internal partners and with EDA vendors in a flexible manner. This is a remote internship starting in June 2024 for 6 months. #DesignEnablement Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Digital circuit design, including CMOS combinatorial logic and sequential element design and layout.
- Understanding of device physics.
- Python programming and automation skills with years of experience in one or more areas of VLSI Design Automation (Physical Design Automation, Simulation, Timing Analysis, Reliability Analysis).
- Collaboration skills across geographically distributed teams and being able to handle ambiguity while developing expertise in new areas and delivering quantifiable results will be key to the success in this role.
- Experience with Industry standard ASIC tools
- Design Compiler, Genus, Tempus, ICV
- Experience in digital circuit design, front end model creation and functional verification.
- Digital circuit design, including CMOS combinatorial logic and sequential element design and layout.
- Experience with standard cell library characterization, liberty models and cross validations with front end models and liberty models.
- Experience working with EDA vendors to drive new features and capabilities.
- Knowledge of industry-standard EDA tools for VLSI circuit and layout design.
- Experience working in the Linux environment and its development tools.
- Standard cell level PPA modeling, simulation, and ROI analysis.
- Experience in CMOS power modeling and cell level optimization.
- CMOS and standard cell level device variation and Aging analysis.
- Engineering acumen and analytical skills.
- Debugging skills.
- Customer oriented and able to work in a dynamic environment. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art
- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
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Standard Cell Design Engineer Intern - Boise, United States - Idaho State Job Bank
Description
Standard Cell Design Engineer Intern at Intel in Boise, Idaho, United States Job Description Job Description The Production Libraries Group is looking for an intern to work in the area of standard cell library design and validation using Intel latest process technology for use by Intel CPU, Atom, Graphics, mixed signal IPs, Client, Sever, Chipset projects and IFS Foundry customers.
The successful candidate will be part of the Production Libraries team responsible for standard cells validation enablement doing EDA tools execution, validation automation development and maintenance, and design issues resolution.
Responsibilities include, but are not limited to:
Traits we're looking for in a candidate:
Minimum Qualifications:
Candidate must be pursuing a MS degree or PhD degree in the field of Electronics Engineering or Hardware Engineering, Electrical and/or Computer Science/Engineering or related fields.
6+ months of knowledge/experience in the following:
Preferred Qualifications:
6+ months of knowledge/experience in the following:
$63,000.00-$166,000.00 Salary range dependent on a number of factors including location and experience Working Model This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. This role may also be available as our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. To view full details and how to apply, please login or create a Job Seeker account
Standard Cell Design Engineer Intern professionals in Boise
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Christopher Verner
Channel Sales Executive & Solution Architect