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    FPGA Verification Engineer - Santa Clara, CA, United States - Arista Networks

    Arista Networks
    Arista Networks Santa Clara, CA, United States

    4 weeks ago

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    Description
    Company DescriptionArista Networks is a fast-growing company and an industry leader in the ethernet switch industry.

    Our switch systems have touched every corner of the market - from the data centers of the world's largest cloud-computing companies, to your local university's server room, and every application in between.

    We design virtually all of the hardware and software that goes into our products and it's a badge we wear proudly.

    This wouldn't be possible without the likes of talented engineers who are given the opportunity to fully lead their own projects and the freedom to think outside the box.

    Whether you are an intern, a junior engineer or someone who's been around the block, one thing is for certain - you will leave your mark.
    This position requires to be onsite in Santa Clara, CAJob DescriptionWe are looking for a motivated individual to join our FPGA Design Team at our headquarters in Santa Clara, CA, in the heart of Silicon Valley.

    In this position, you will be responsible for designing test bench, simulating, and testing FPGA RTL code that forms the backbone of our next generation systems.


    Job Responsibilities:

    Create and maintain test benches in Verilog/SystemVerilogCreate BFM, RTL models for new and existing designsDevelop the verification test plans and test casesReview the design functional coverageConcepts and Skills: Data and control architectures of a modern ethernet switch, including chip IO interfaces such as Interlaken, Ethernet PHY/MAC, PCIe, SMBus, SPI, MDIO, JTAG, etc.

    Protocols using Ethernet, such as PTP, SFlow, POE, etc.

    Simulation software for FPGA functional verificationQualifications2-4 years of designing Verilog/SystemVerilog RTL codeProficient in design verification tools and languages (SystemVerilog, SVA, Modelsim, Perl, Python, Unix shell scripts)Experience in the chip level verification environment setups, code/functional coverage collectionMotivated, passionate, with sense of urgency and commitment to achieve the targeted goalsStrong scripting, debugging and problem solving skillsExcellent in-person, video, and written communication skillsAdditional InformationThe new hire base pay for this role has a salary range of $130,000 to $180,000.

    The actual salary offered will be based on a wide range of factors, including skills, qualifications, relevant experience, and US location.

    The salary range provided reflects the base salary and in addition may also be eligible for discretionary Arista bonuses, commissions, equity, and benefits including medical, dental, vision, well-being, tax savings, and income protection.

    All your information will be kept confidential according to EEO guidelines.


    SummaryType:
    Full-timeFunction: EngineeringExperience level: Mid-Senior LevelIndustry: Computer Networking
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