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SoC Design Engineer - Boise, United States - Idaho State Job Bank
Description
SoC Design Engineer at Intel in Boise, Idaho, United States Job Description Job Description Do you want to engineer the future?? Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth.? So join us, and help create the next generation of technologies that will shape the future for decades to come.? We are designing future generations of high-performance Intel E-Core CPUs using the most advanced and innovative process technologies.? These CPUs help power the latest generation of Intel laptops and desktops, 5G base stations, micro-servers, Chromebooks for students and other Artificial Intelligence and Machine Learning devices.
+ Develop and test flows using Engineering Design Automation (EDA) tools in 1 or more areas of Design Synthesis, Automatic Place and Route, Static Timing Analysis (STA), Formal-Equivalence Checking, Electrical Rule Checks (ERC), Static Noise analysis, Circuit Power Estimation, Layout Verification, Power-Rail Integrity, Extraction, ECO, or SPICE circuit simulation . + Interface with CPU Design Team to create or test flows/scripts to analyze design methodologies for cell-based and/or transistor-based designs. + Validate PDK (process design kits), library files and other collaterals used for either standard cell or custom-transistor design, layout, and signoff with EDA CAD tools. + Create flows/scripts to analyze, test and improve design methodologies, including through Machine Learning, and look for inefficiencies. + Document, provide training and help with developing specifications & usage guidelines .
The ideal candidate should exhibit the following behavioral traits:
+ Good inter-personal, clear communication and good teamwork skills + A can-do attitude driven by research and thriving on challenges. + Self-motivated with strong problem-solving skills Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications(must haves)
Candidate must have a bachelor's degree in electrical/Computer Engineering or related field and 5+ years of experience OR a Master's degree in Electrical/Computer Engineering or related field and 4+ years of experience OR a PhD in Electrical/Computer Engineering or related field and 2+ years of experience in:
Design principles and techniques in VLSI back-end design, custom-circuit (transistor) design and/or memory design Design Automation and/or CAD for CPUs or SOCs, including timing closure of gate level and/or transistor level designs (RLS, SPICE) in advanced CMOS processes Backend design EDA tools Synopsys, Cadence and/or Mentor Graphics - logic synthesis, design-for-test, place-and-route, clock tree synthesis, timing/power optimization, ECO, static timing analysis, Spice circuit simulation, statistical variation analysis, noise, cross-talk, OCV, reliability verification, formal equivalence verification, and ERC flows (logic synthesis/UNIX/Linux environments) and Perl/Tcl/Shell/Python scripting Preferred Qualifications (Good to have) + Machine-learning methods to solve complex problems dealing with automation of circuit design to aid in performance and power improvement.
+ Detailed knowledge in Cadence Innovus, Genus, Tempus OR Synopsys Fusion Compiler and Primetime tools + Familiarity with advanced programming - algorithms and data structures used in EDA tools.
Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products.
From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations.
DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams.As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Other Locations US, OR, Hillsboro; US, CA, Folsom; US, CA, Santa Clara Covid Statement Intel strongly encourages employees to be vaccinated against COVID-19.
Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in US, California: $139,480.00-$209,760.00 Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs. To view full details and how to apply, please login or create a Job Seeker account