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    Verification Engineer - Fremont, United States - Happiest Minds Technologies Limited

    Happiest Minds Technologies Limited
    Happiest Minds Technologies Limited Fremont, United States

    1 week ago

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    Description

    Verification Engineer

    Fremont, CA

    BSEE or BSCS, or equivalent

    • 5+ years of ASIC/FPGA verification experience using SystemVerilog / UVM
    • Must have experience with:
      • Verification flow using Questa simulation
      • Developing verification plans
      • Designing and implementing SystemVerilog / UVM test benches for constrained-random verification
      • Developing functional coverage models
      • Writing and debugging directed and random test cases
      • Experience with automation/scripting (Python, Perl, sed, awk, tcl/tk, sh)
    • Experience with the following is a plus
      • C programming desirable. SystemC and C++ used in conjunction with chip design and verification
      • Experience with Formal verification / property-checking
      • Experience with emulation or FPGA prototyping
      • Knowledge of standard protocols (such as PCIe)
      • Knowledge of DO-254
      • FPGA experience
    • Good communication skills

    Job Description:

    • Deliver consulting services covering functional verification flow implementation.
    • Work with customer to implement and deploy advanced verification methodologies.


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