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ASIC Engineer
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ASIC Verification Engineer
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ASIC Design Engineer
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ASIC Verification Engineer
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ASIC Verification Engineer
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ASIC Design Engineer
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ASIC Design Engineer
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ASIC Verification Engineer
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European Recruitment San Jose, United StatesASIC Verification Engineer- · System Verilog / UVM · We are partnered up with a well-established Semiconductor organisation who enable state of the art perception for autonomous vehicles who are looking for Senior ASIC Verification Engineer to join their team in California. · ...
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ASIC Verification Engineer
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Recogni San Jose, United StatesAbout Recogni: · Artificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different environments with the ability to quickly learn and then solve complex problems. Reco ...
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ASIC Verification Engineer
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Cisco San Jose, United StatesWho We Are · The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of var ...
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ASIC Verification Engineer
1 week ago
Cisco San Jose, United StatesWho We Are · The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of vari ...
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ASIC Design Engineer
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ASIC Design Engineer
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ASIC Design Engineer
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ASIC Verification Engineer
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ASIC Design Engineer
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ASIC Verification Engineer
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Penn Foster Inc Santa Clara, United StatesThe NVIDIA Clocks Team is looking for an ASIC Verification engineer to validate CPU, GPU and SOC clocks design. Our team is committed to delivering high-quality clocking and reset logic to various units in SOC and GPU ASIC. The complexity of the clocks and resets has increased ma ...
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ASIC Design Engineer
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P. Chappel Associates Inc Santa Clara, United States· Front-End ASIC Lead Design Engineer - Santa Clara, CA · Unique opportunity to join an established international company in their US expansion. Working from the US headquarters, you will have the ability to be an impact player working with other exceptionally talented people. T ...
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Senior ASIC Engineer
7 hours ago
NVIDIA Santa Clara, United StatesWe are now looking for a motivated Senior ASIC Engineer, Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role in improving the netlist and timing quality of our designs and if you are a self-starter and highly motivated individual wh ...
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Senior ASIC Engineer
4 days ago
NVIDIA Santa Clara, United StatesWe are now looking for a motivated Senior ASIC Engineer, Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role in improving the netlist and timing quality of our designs and if you are a self-starter and highly motivated individual wh ...
Senior Manager, ASIC Engineering - San Jose, United States - Conductor
Description
What You'll Do
High performance computing, AI / ML have resulted in rapid transformation of semiconductor industry especially in datacenter, automotive , networking etc domains.
This Senior Manager, Asic Engineering position will be responsible for overall chip design execution from spec to silicon, so the candidate should be familiar with Architecture / Micro Architecture / Synthesis, DFT, Design Verification, Physical Design, Timing Signoff etc and should be domain expert in one or more of the above domains, especially DFT, Test , ATPG , Binning, Yield, in system test, debug and diagnostic needs of the design with heavy customer Interactions
Location :
Onsite at our San Jose headquarters 5 days a week
Report to:
Senior Director - ASIC
Job #: 42022
Solid experience in full chip DFT architecture / spec creation for monolithic / 2.5 D / 3D designs / product level testing
Solid experience in DFT and Test insertion , especially big die implementation
Solid experience in JTAG protocols, Scan, and BIST architectures like memory BIST, IO BIST, LBIST, Streaming Scan Network
Solid knowledge of NOC ( Network on Chip from Netspeed / Arteris )
Solid experience in post silicon validation , validating and debugging test vectors on ATE during silicon bringup.
Solid experience in writing DFT timing constraints
Solid experience of working closely with STA and PD engineers to close timing in test mode
Solid experience in generating, verifying anf debugging test vectors
Excellent communication skills
Ability to work independently and mentor junior team members
Complete other responsibilities as assigned.
What You Bring
Bachelors in Electrical Engineering, Physics, or related Physical Science with 15+ years of experience or Masters in Electrical Engineering, Physics or related Physical Science with 13+ years of Industry Experience or PhD in Electrical Engineering, Physics, or related Physical Science with 10+ years of Industry Experience Preferred.
Experience in in DFT Insertion in ASIC or SoC Design, with hands on experience in large complex projects.
Strong knowledge of DFT insertion, simulation in SoC / CPU / GPU Designs.
Comfortable working with internal teams, external teams, and customers.
Highly passionate and energetic.
Excellent communication skills.
Experience of having worked on monolithic / chiplet /2.5D / 3D designs with D2D and HBM2/3 memory interfaces will be a plus
Project management and deep technical customer interaction.
Frequent customer and partner visits to include Domestic and International travel.
Strong customer orientation, good communication and presentation skills.
You're inclusive, adapting your style to the situation and diverse global norms of our people.
An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
Innovative and creative, you proactively explore new ideas and adapt quickly to change.
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