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ASIC Design Engineer - San Jose, United States - TCWGlobal
Description
Job Description
Job DescriptionASIC Design Engineer
Remote, USA
W2 Contract 6 Months
$111/hr + Benefits
We are a leading provider of smart, connected, and secure embedded control solutions. Our solutions serve more than 125,000 customers across the industrial, automotive, consumer, aerospace and defense, communications, and computing markets.
As a member of our engineering community, your primary responsibility will be to verify ASIC implementations for timing and ASIC Design Audits (Lint, CDC, DFT, etc.) at the block and full chip level.
Duties & Responsibilities:
General ASIC development
Participate in the RTL implementation, synthesis, formality check as well as ECOs
Support post-layout timing closure and verification
Detailed ASIC Back-End Development
Support the design team to develop Block / Full Chip Level Constraints, verify timing constraints with industry standard tools and run synthesis.
Support LINT, clock-domain crossing, and reset-domain-crossing analysis.
Perform Static Timing Analysis both pre-layout and post-layout.
Support any Timing of Functional ECOs as needed.
JOB Requirements
Strong Experience in RTL design, design verification, synthesis (Genus experience strongly preferred) & formal verification
Strong Experience in Tempus and Verilog simulation tools
Strong Experience in LINT, CDC, and RDC (SpyGlass experience strongly preferred )
Able to write clean, readable presentations
Self-motivated, proactive team player
Ability to work to schedule requirements
Education Required
Bachelors/Masters in electrical engineering, Computer Engineering or Computer Science.
Experience Required
Minimum of 10 years of proven silicon design experience in ASIC Implementation
5+ years of Cadence Tempus experience
Beneficial Experience
FPGA and ASIC System On Chip Design Experience
TCWGlobal is an equal opportunity employer. We do not discriminate based on age, ethnicity, gender, nationality, religious belief, or sexual orientation.
