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    Defect Control Manager - Phoenix, United States - Taleo BE

    Taleo BE
    Taleo BE Phoenix, United States

    6 days ago

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    Description

    Job Details:

    Job Description:


    Fab Sort Manufacturing (FSM) is responsible for the production of all Intel silicon using some of the world's most advanced manufacturing processes in fabs in Arizona, Ireland, Israel, Oregon and 2 new greenfield sites in Ohio and Germany.

    As part of Intel's IDM2.0 strategy, FSM is rapidly expanding its operation to deliver output for both internal and foundry customers with state-of-the-art technologies arriving in high-volume manufacturing at a 2-year cadence going forward.

    Intel recently created HVM Global Yield organization in FSM to strengthen its yield operation and enable fast-paced yield ramp-up in early HVM phases for each technology in collaboration with Technology Development team and FSM fab managers.


    This job requisition is to seek Defect Control team manager in FSM HVM Global Yield organization, reporting to Director of Defect Engineering.

    The selected candidate will build and lead a team in HVM Global Yield organization and work with other leaders in the org, fab module/yield managers and TD leaders to support yield ramp-up and process optimization in early production stage, supporting internal and external customers.

    Defect Control team manager responsibilities include (but not limited to):
    Build and lead Defect Control team in FSM HVM Global Yield organization to execute HVM yield roadmap.

    Collaborate with Technology Development team and Process Integration team to import and setup new technology to production fabs across the globe.

    Work with Process Integration teams, Yield Analysis team and FSM Yield managers to lead fast paced yield ramp-up in high-volume manufacturing phases.

    Review, compare, and propose wafer inspection tool selection options in production line with comprehensive quantitative analysis.

    Set up and optimize wafer inspection steps in process flow to ensure detection of yield detracting defects in line at step.

    Design and execute production wafer inspection strategy to protect yield and quality at maximum productivity and lowest cost.
    Build, maintain and update defect library per technology and per product.

    Identify systematic defect issues and drive mitigation actions with Defect Reduction team in defined timeline to meet committed production yield targets.


    Candidate should possess the following behavioral skills:
    Problem-solving and project/program management experience with strong self-initiative and self-learning capabilities.
    Demonstrated interpersonal skills to perform at leadership role including influencing, engaging, and motivating.
    Proven track record of working across organization through matrix structures to accomplish strategic objectives with conflicting priorities.
    Must demonstrate strong communication skills.


    Qualifications:
    Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.


    Minimum Qualifications:
    Bachelor's degree in engineering or science area.
    8+ years of experience in advanced node semiconductor industry in Defect engineering or Failure analysis.

    3+ years of people leadership experience to manage and direct an organization of 10+ process/defect engineers in fast-paced high-volume semiconductor manufacturing environment to drive yield, technology, quality, output and cost.

    Strong understanding on defect mechanism and yield impact in semiconductor high-volume production and 5+years' experience in driving down D0.
    5+ years of experience with various defect inspection tools in high-volume semiconductor manufacturing.
    5+ years of experience in wafer inspection recipe setup and optimization.
    3+ years of experience in semiconductor high-volume production defect inspection line management.


    Preferred Qualifications:
    Master's or Ph.
    D. degree in Physics or Materials Science major.
    Understanding on layout-sensitive defects and knowledge of scan diagnosis and other defect analysis skills.
    Experience in FinFET technology development or high-volume manufacturing.
    Working knowledge in module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology. Skills to develop improvement projects at module level to improve process for reduced defectivity and improved yield.
    Knowledge of module tool impacts to defects, inline parametric and yield through PM life while understanding upstream and downstream impacts to other tools


    Job Type:
    Experienced Hire


    Shift:
    Shift 1 (United States of America)


    Primary Location:
    US, Arizona, Phoenix


    Additional Locations:

    Business group:

    As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.


    Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.


    Posting Statement:

    All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

    Position of Trust N/A
    Work Model for this Role

    This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

    In certain circumstances the work model may change to accommodate business needs.
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