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    ASIC Physical Design Engineer - San Jose, United States - Infinera

    Infinera
    Infinera San Jose, United States

    2 days ago

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    Description

    CA Pay Range (Annual):

    At Infinera, your base pay is one part of your total compensation package. Your actual base pay will depend on your skills, qualifications, experience, and location. This role may be eligible for equity grants, discretionary bonuses, or commission payments. The amount of these incentives is based on the terms of the Company's incentive plans, the Company's financial performance, and/or individual employee job performance.

    Infinera also offers paid leave, medical,

    dental, and vision coverage, 401(k), life, and disability insurance and to

    eligible employees.

    Infinera is a global supplier of innovative networking solutions. Our customers include the leading service providers, data center operators, internet content providers (ICPs), cable operators, enterprises, and government agencies worldwide, including 9 of the top 10 Tier 1 service providers and 6 of the top 7 ICPs. We design, develop and deliver hardware and software for fiber-based connectivity solutions that span access, aggregation, metro, long haul, and submarine network. Our industry-leading, trendsetting edge-to-core solutions provide the foundation for many of the world's largest and most demanding networks that generate billions in service revenue for our customers.

    Title: ASIC Physical Design Engineer

    Location: San Jose, CA

    • Your Key Responsibilities Would Include:
    • Perform physical implementation steps including floor planning, place and route, power/clock distribution for congestion analysis and timing closure at block level as well as full chip
    • Work with logic designers to drive feasibility studies and explore design trade-off for physical design closure
    • Perform technical evaluations of vendor, process nodes and IP and provide recommendations
    • Develop physical design methodologies and automation scripts for various implementation steps from Synthesis to GDSII
    • Perform static timing analysis, create timing constraints and validation, critical path analysis, timing closure and timing sign-off

      Education & Experience Necessary For Success:
    • 5+ years of experience in ASIC physical design flow and methodologies in 5/7nm and 16nm process nodes
    • Has solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design
    • Experience with EDA Place & Route tools like ICC2 or Innovus or similar tools and Timing tools like Primetime or similar
    • Scripting experience in TCL, python or perl
    • Candidates must have a Bachelor's Degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics with very good academics..
    #LI-SR2

    Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law. Infinera complies with all applicable state and local laws governing nondiscrimination in employment.
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