-
Verification Engineer
1 week ago
Synopsys Sunnyvale, United StatesOur Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world's broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabiliti ...
-
Verification Engineer
1 week ago
ACL Digital Santa Clara, United StatesJob Description : We need someone familiar with UVM to run and debug tests. If they are capable, we will also ask them to write some testbench modules and components. Perhaps the most important thing is that they are diligentand good at communicating what they find and where the ...
-
Design Verification Engineer
4 days ago
Meta Inc Sunnyvale, United StatesMeta's Reality Labs(RL) focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta RL Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine lear ...
-
Design Verification Engineer
1 week ago
META Sunnyvale, United StatesSummary: · Reality Labs focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta's Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learn ...
-
Design Verification Engineer
1 week ago
NR Consulting Sunnyvale, United StatesJob Title: Design Verification Engineer · Duration: 12 mos + Possible extension · Location: : Sunnyvale CA · Description: · •Strong DV background (test plan development, test writing, SystemVerilog, UVM) · Duties:Write and augment existing testplans. · Implement testbench and s ...
-
Design Verification Engineer
1 day ago
Baidu Sunnyvale, United StatesDo you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry and have the desire to solve them? Do you want to work with a world-class team to explore the fast-growing AI hardware opportunities and impact on AI industry? ...
-
Formal Verification Engineer
2 days ago
NR Consulting Sunnyvale, United StatesJob Title :- Formal Verification Engineer · Job Location :- Sunnyvale, CA · Position Type:- Contract · Education & Experience Required: · •Knowledge of Formal verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, · connectivity etc · •5+ ...
-
Electrical Verification Engineer
1 week ago
Midas Consulting Sunnyvale, United StatesROLES & RESPONSIBILITIES:Define electrical verification methodologies for each of the different systems by working with researchers, architects, and the design teams · Define and track detailed test plans for the different modules and top-level systems · Define, architect, design ...
-
Verification Engineer
6 days ago
Cynet Systems Inc Santa Clara CA, United States Full time, contractJob Role Verification EngineerJob Type Contract Job Location Santa Clara CA (or) Job DescriptionVerification Engineer for Memory Controller · • Significant UVM SystemVerilog experience in complex test-benches · • Experience working with DRAM controller PHYs memory models is prefe ...
-
Senior Verification engineer
1 week ago
TWO95 International Sunnyvale, United StatesDuration: 6+ Months · Rate: $Open · Skills: UVM and System Verilog · Requirement:. · • 5+ or more years of proven experience on ASIC / SoC / IP Verification. · • Strong experience in SystemVerilog and UVM verification methodologies · • Proficiency in Object Oriented programming, ...
-
IP Verification Engineer
1 week ago
Triple Crown Services Mountain View, United StatesTriple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who en ...
-
Silicon Verification Engineer
6 days ago
BrickRed Systems Mountain View, United StatesWe are seeking a highly skilled Silicon Verification Engineer to join our team. The ideal candidate will be responsible for writing Silicon verification tests, running and debugging tests, and ensuring the overall quality and functionality of our silicon designs. This role requir ...
-
Design Verification Engineer
1 week ago
QuEST Global Mountain View, United StatesDesign Verification Engineer · San Jose CA · JOB DESCRIPTION · Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc. · ? Strong HVL (UVM or SystemVerilog with OVM), C/C++, Perl, TCL programming skills. ...
-
DfT Verification Engineer
1 week ago
Oho Group Ltd Mountain View, United StatesA RISC-V start up is looking for a DFT Verification Engineer who wants to accelerate their career within a hugely accelerating business · My client is circa 400 people worldwide and has lured some of the top engineers from Apple & some of the household named Semi-Conductors. · ...
-
Silicon Verification Engineer
3 days ago
BrickRed Systems Mountain View, United StatesWe are seeking a highly skilled Silicon Verification Engineer to join our team. The ideal candidate will be responsible for writing Silicon verification tests, running and debugging tests, and ensuring the overall quality and functionality of our silicon designs. This role requir ...
-
CPU Verification Engineer
2 weeks ago
BrickRed Systems Mountain View, United StatesWe are seeking a highly skilled Silicon Verification Engineer to join our team. The ideal candidate will be responsible for writing Silicon verification tests, running and debugging tests, and ensuring the overall quality and functionality of our silicon designs. This role requir ...
-
IP Verification Engineer
1 day ago
Triple Crown Services Mountain View, United StatesTriple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who en ...
-
Design Verification Engineer
1 day ago
Acceler8 Talent Mountain View, United StatesAcceler8 Talent has recently partnered with a company that is redefining AI hardware, focusing on maximizing performance for large language models (LLMs) like GPT. With a commitment to cost efficiency and optimizing performance-per-dollar, their technology offers competitive late ...
-
DfT Verification Engineer
5 days ago
Oho Group Ltd Mountain View, United StatesA RISC-V start up is looking for a DFT Verification Engineer who wants to accelerate their career within a hugely accelerating business · Is this your next job Read the full description below to find out, and do not hesitate to make an application. · My client is circa 400 peop ...
-
Silicon Verification Engineer
1 week ago
Ursus Inc Mountain View, United States Full timeJOB TITLE: Silicon Verification Engineer · LOCATION: Santa Clara CA , Austin TX, Portland OR, Fort Collins CO · SALARY: K annual · Responsibilities Work closely with architecture and RTL designers on verifying the functionality correctness of the design · Reviewing Architectu ...
Design Verification Engineer - Sunnyvale, United States - Baidu
Description
Do you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry and have the desire to solve them? Do you want to work with a world-class team to explore the fast-growing AI hardware opportunities and impact on AI industry?Were looking forward to you joining us to collaborate, contribute, and revolutionize AI silicon and system.
Your job responsibilities as a Design Verification Engineer will help the team to verify the functionality of Baidu's AI SoC at both block level and SoC level.
You will help on UVM Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development.
Run RTL and gate level functional verification, debug failures, lead bug tracking, and analyze and close coverage.Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model.
Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases, reference model, coverage model and automation of regression suite.Support emulation and silicon bring up debug with your smart ideas to duplicate the problem in simulation.
QualificationsMinimum 5 years of experience of UVM based verification on a significantly complex project.
Advanced knowledge of standard ASIC design and verification flows, simulation and testbench development.
Advanced knowledge of System Verilog and the UVM methodology.
Solid verification skills in problem solving, constrained random testing, coverage closure, gate level simulations, X propagation.
Good practice of one scripting language (Perl, Python, Tcl) no preference.
SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache).Familiar with C/C++.Formal Verification (Model Checking, Equivalence Checking).Excellent communication skills in both English and Chinese.
Culture Fit:
Mission alignment:
If you want to be part of a team to accomplish this great mission, we will provide you the best possible platform to do that
Self-directed:
We work best with people that are driven, motivated, and aspire to greatness
Hungry to learn:
We are eager to see you learn new skills and grow
Team orientation:
We work in small, fast-moving teams. We watch out for each other and go after big goals together as a team.