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Verification Engineer
1 hour ago
Collabera Sunnyvale, United States· Home · Search Jobs · Job Description · Verification Engineer · Contract: Sunnyvale, California, US · Salary: $50.00 Per Hour · Job Code: · End Date: · Days Left: 27 days, 3 hours left · Apply · Job Summary: · Working under limited supervision, performs moderate risk/mo ...
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Verification Engineer
1 day ago
Collabera Sunnyvale, United StatesHome · Search Jobs · Job Description · Verification Engineer · Contract: Sunnyvale, California, US · Salary: $50.00 Per Hour · Job Code: · End Date: · Days Left: 26 days, 3 hours left · Apply · Job Summary:Working under limited supervision, performs moderate risk/moderat ...
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Software Verification Engineer
5 days ago
Rangam Sunnyvale, United StatesJob requirements: · Bachelor's degree in software engineering, computer science, or a related engineering field with 2+ years working experience. · Working from requirement specifications to develop, maintain, and update test procedures and test scripts. · Develop automation veri ...
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Design Verification Engineer
5 days ago
Quest Global Sunnyvale, United StatesHello , · Hope you doing good · Job Profile description. · location - Sunnyvale, California, United States · 7+ YOE in DV. · IP verification experience using SV/UVM methodology. · Excellent coding and debugging skills, should have exp. In coding various TB components. · AMBA pro ...
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Hardware Verification Engineer
6 days ago
BrickRed Systems Mountain View, United StatesWe are seeking an experienced and highly skilled Silicon Verification Engineer to join our dynamic team. The ideal candidate will have a robust background in ASIC design and verification, with a strong proficiency in SystemVerilog and UVM methodologies. You will be responsible fo ...
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Design Verification Engineer
2 days ago
SpaceX Sunnyvale, United StatesDesign Verification Engineer (Silicon Engineering) at SpaceX · Sunnyvale, CA · SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologie ...
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SOC Verification Engineer
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Apple Sunnyvale, United StatesSOC Verification Engineer · Sunnyvale,California,United States · Hardware · Would you like to join Apples growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highl ...
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Design Verification Engineer
1 day ago
Cynet Systems Inc. Sunnyvale, United StatesSkills, Experience, Education and Training: · Advanced knowledge of HVL methodology (UVM). · Expertise in HVL and HDL (System Verilog, Verilog). · Experience defining coverage space and writing coverage model. · Experience with System Verilog Assertion (SVA) is a plus. · Team pl ...
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Senior Verification engineer
1 hour ago
TWO95 International Sunnyvale, United StatesHi, · Title: Lead / Senior Verification engineer · Location: San Jose, CA / Santa Clara, CA · Duration: 6+ Months · Rate: $Open Skills: UVM and System Verilog Requirement:. · • 5+ or more years of proven experience on ASIC / SoC / IP Verification. · • Strong experience in S ...
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Verification Engineer
3 days ago
Collabera Sunnyvale, United StatesHome · Search Jobs · Job Description · Verification Engineer · Contract: Sunnyvale, California, US · Salary: $50.00 Per Hour · Job Code: · End Date: · Days Left: 27 days, 3 hours left · Apply · Job Summary:Working under limited supervision, performs moderate risk/moderat ...
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Accelerator Verification Engineer
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Ursus Inc Santa Clara, United StatesJOB TITLE: Accelerator Verification Engineer · LOCATION: (US) Santa Clara CA , Austin TX, Portland OR, Fort Collins CO · QUALIFICATIONS: · Join a cutting-edge hardware startup in Silicon Valley as a Silicon Verification Engineer. Our mission is to reimagine silicon and create ...
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Silicon Verification Engineer
3 weeks ago
BrickRed Systems Mountain View, United StatesWe are seeking a highly skilled Silicon Verification Engineer to join our team. The ideal candidate will be responsible for writing Silicon verification tests, running and debugging tests, and ensuring the overall quality and functionality of our silicon designs. This role requir ...
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Design Verification Engineer
3 weeks ago
Acceler8 Talent Mountain View, United StatesAcceler8 Talent has recently partnered with a company that is redefining AI hardware, focusing on maximizing performance for large language models (LLMs) like GPT. With a commitment to cost efficiency and optimizing performance-per-dollar, their technology offers competitive late ...
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Design Verification Engineer
6 days ago
GAC Solutions Santa Clara, United StatesTitle - Design Verification Engineer · Location - Santa Clara, CA (Onsite) · Duration - 6+ Months · "Desired Qualifications: · • Over 7 years of hands-on experience in pre-silicon design verification. · • Proficient in scripting with C-shell, along with mastery in Verilog-HDL an ...
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design verification Engineer
1 week ago
Diverse Lynx Mountain View, United StatesPosition: design verification Engineer · Location: Mountain view, CA · Job Type: Fulltime/contract · Requirement For Performance DV · DV engineer with 5- 8 years of experience. · Traditional DV (SV/UVM )as well as performance DV. · For performance DV, experience with Python sc ...
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Design Verification Engineer
1 week ago
Understanding Recruitment Mountain View, United StatesAcceler8 Talent has recently partnered with a company that is redefining AI hardware, focusing on maximizing performance for large language models (LLMs) like GPT. With a commitment to cost efficiency and optimizing performance-per-dollar, their technology offers competitive late ...
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silicon verification engineer
1 week ago
Randstad Mountain View, United Statessilicon verification engineer. · mountain view , california · posted 1 day ago · job details · summary · $ $72.72 per hour · contract · bachelor degree · category computer and mathematical occupations · reference · job details · job summary: · Define, document, and impleme ...
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Firmware Verification Engineer
2 days ago
Apple Cupertino, United StatesFirmware Verification Engineer · Santa Clara Valley (Cupertino),California,United States · Hardware · Do you have a passion for invention and self-challenge? As part of an elite modem team, we'll craft sophisticated Infrastructure and Framework to validate embedded firmware th ...
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Formal Verification Engineer
2 days ago
Apple Cupertino, United StatesFormal Verification Engineer · Cupertino,California,United States · Hardware · Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufactu ...
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Meta Sunnyvale, CA, United StatesMeta's Reality Labs(RL) focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta RL Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine lear ...
Design Verification Engineer - Sunnyvale, United States - Baidu
Description
Do you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry and have the desire to solve them? Do you want to work with a world-class team to explore the fast-growing AI hardware opportunities and impact on AI industry?We're looking forward to you joining us to collaborate, contribute, and revolutionize AI silicon and system.
Description
We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive in this highly technical environment.
Your job responsibilities as a Design Verification Engineer will help the team to verify the functionality of Baidu's AI SoC at both block level and SoC level.
You will help on UVM Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development.
Run RTL and gate level functional verification, debug failures, lead bug tracking, and analyze and close coverage.Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model.
Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases, reference model, coverage model and automation of regression suite.Support emulation and silicon bring up debug with your smart ideas to duplicate the problem in simulation.
Qualifications
Minimum 5 years of experience of UVM based verification on a significantly complex project.
Advanced knowledge of standard ASIC design and verification flows, simulation and testbench development.
Advanced knowledge of System Verilog and the UVM methodology.
Solid verification skills in problem solving, constrained random testing, coverage closure, gate level simulations, X propagation.
Good practice of one scripting language (Perl, Python, Tcl) no preference.
SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache).
Familiar with C/C++.
Formal Verification (Model Checking, Equivalence Checking).
Excellent communication skills in both English and Chinese.
Culture Fit:
Mission alignment:
If you want to be part of a team to accomplish this great mission, we will provide you the best possible platform to do that.
Self-directed: We work best with people that are driven, motivated, and aspire to greatness.Hungry to learn:
We are eager to see you learn new skills and grow.
Team orientation:
We work in small, fast-moving teams. We watch out for each other and go after big goals together as a team.
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