- Familiarity with Verilog and SystemVerilog is a plus.
- Familiarity with Xcelium or Modelsim or Synopsys VCS is required.
- Good communications skills are required and prior customer support experience is a plus.
- Experience writing or maintaining the script or Makefile that builds the simulation program from RTL is a plus.
- Familiarity with Verdi, Indago and/or SimView is a plus.
- Scripting/coding abilities in Python/Perl is required.
- Knowledge of C/C++ or any other OOP programming language is a plus.
- Proven track record dealing with customers internal or external would be a plus.
- Experience driving verification methodologies/solutions with customers is a plus.
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CAD Engineer-Design Verification Flows and Methodology - Boston, United States - Apple
Description
SummaryPosted: Jan 3, 2024
Role Number:
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices In the CAD organization, you will get to create new software and technologies that will enable other Apple engineers to create products for millions of customers across the world
Key Qualifications
DESCRIPTION: As a member of our CAD team, you will develop, maintain, and enhance existing sophisticated software systems for regression-testing Apple's silicon designs in software simulation, to find and report defects in our chip designs, and thus ensure that Apple tapes-out world-class silicon. Your experience and innovative ideas will inform the design of the next generation of these regression systems. Your experience and insight, skill at diagnosing the root cause of complex problems, and ability to guide engineers who come to you with problems will be important contributions to an extended CAD team that comprehensively supports Apple's DV and chip design engineering efforts. You will work closely with EDA vendors to incorporate new capabilities of their commercial tools, and to resolve problems. CORE RESPONSIBILITIES: - Develop, maintain, and enhance an existing system for regressing RTL - Interact with DV team to help understand their problems and propose solutions to solve them. - Ability to offer unique solutions that are scalable for user problems. - Propose new methodology changes to aid smart verification for next generation system on chip design. - Implement new functionality to solve emerging problems or to optimize already existing methods. - Ability to handle complex development tasks, testing the solution and deployment to engineering teams is required - Mentor and provide guidance to others if needed - Leverage existing solutions, custom and industry-standard, and applying to solving problem at hand. - Role involves debugging vendor tool problems and driving methodology changes with them to aid next generation verification. - Drive smart verification methodology with customers and vendors.
Education & Experience
Minimum requirement of BS + 10years of relevant industry experience.
Additional Requirements
Additional Requirements
