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CAD Engineer-Design Verification Flows and Methodology - Boston, United States - Apple
![Apple background](https://contents.bebee.com/companies/us/apple/background-gPcF9.png)
Description
SummaryPosted:
Jan 3, 2024
Role Number:
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC).
Key Qualifications
Familiarity with Xcelium or Modelsim or Synopsys VCS is required.
Good communications skills are required and prior customer support experience is a plus.
Experience writing or maintaining the script or Makefile that builds the simulation program from RTL is a plus.
Familiarity with Verdi, Indago and/or SimView is a plus.
Scripting/coding abilities in Python/Perl is a plus.
Knowledge of C/C++ or any other OOP programming language is a plus.
Description
As a member of our CAD team, you will develop, maintain, and enhance existing sophisticated software systems for regression-testing Apple's silicon designs in software simulation, to find and report defects in our chip designs, and thus ensure that Apple tapes-out world-class silicon.
Your experience and insight, your skill at diagnosing the root cause of complex problems, and ability to guide engineers who come to you with problems will be important contributions to an extended CAD team that comprehensively supports Apple's DV and chip design engineering efforts.
You will work closely with EDA vendors to incorporate new capabilities of their commercial tools, and to resolve problems.CORE RESPONSIBILITIES:
Minimum requirement of BS + 3 years of relevant industry experience.
Additional Requirements
Additional Requirements
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