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    Staff Structural Design - Santa Clara, United States - Workday

    Workday
    Workday Santa Clara, United States

    1 week ago

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    Description

    Job Details:

    Job Description:
    Do Something Wonderful
    Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our

    YouTube Channel

    or the links below
    Life at Intel
    Diversity at Intel

    Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations.

    With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life.

    Join us and help make the future more wonderful for everyone.

    Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs.

    With the first "Open System Foundry" model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient, and sustainable source of supply.

    As a Structural (Physical) Design Engineer Design your responsibilities include:
    Designs, implements, verifies, and supports the enablement and adoption of hardware design tools, flows, and methodologies.
    Defines methodologies for hardware development related to technology node and EDA tool enabling.

    Creates and verifies unique hardware designs, assembles design platforms, and integrates components into hierarchical systems to provide deployment coverage for end-to-end EDA tool testing on new technology nodes.

    Develops, tests, and analyzes engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance.
    Supports development and enhancement of platforms, databases, scripts, and tools flows for design automation.

    Builds deep understanding of digital design, verification, structural and physical layout, fullchip integration, power and performance, clocking, and/or timing to enhance future TFM development.

    Collaborates with EDA vendors on defining and early testing of next generation design tools.

    The Structural (Physical) Design Engineer will exhibit behavioral traits that demonstrate:
    Excellent verbal and written communication and collaboration skills.

    Strong communication and collaboration skills, including a willingness to work with others, and the ability to tolerate ambiguity and highly complex decision environments.


    Qualifications:
    The candidate must have a Bachelor's degree in Computer/Electrical Engineering or Computer Science and 4+ years of experience -OR- a Master's Degree in Computer/Electrical Engineering or Computer Science and 2+ years of experience -OR- a PhD in Computer/Electrical Engineering or Computer Science and 1+ year of experience with the following:

    Hands-on experience with industry standard Cadence or Synopsys tool suite, methodology and flow development.

    Experience with Full-Chip level work such as Floorplanning, PnR, CTS, different clocking techniques for skew and delay balancing, multiple clock complexity, time budgeting, timing closure techniques, PnR congestion analysis, resolving floorplanning issues, UPF (Low power design techniques), layout physical problems, design sign-off tools like and not limited to noise analysis, layout closure, timing and functional eco closure, IR drop analysis etc.

    Experience with RTL to gds2 flow and background with basic device physics.

    2+ years' experience scripting with some or all in csh, Python, tcl, perl, shell etc. to write EDA tools and flows solutions.
    Previous experience with Physical Design (Structural Design) flow/methodology development.
    Experience with 7nm technology or below.

    How to Stand out (Preferred Qualifications):
    Associated with full chip level and multiple tape-outs of complex SoCs.
    Exposure to various industry standard Physical Design and Sign-Off closure tools.
    Understanding of peer domains to Physical Design, viz., RTL, verification, DFx, post-Si etc.

    Amazing Benefits
    Here at Intel, we invest in our people.

    Beyond health, dental, and retirement benefits, Intel's benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment.


    Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program.

    Find more information about our

    Amazing Benefits here :



    Job Type:
    Experienced Hire


    Shift:
    Shift 1 (United States of America)


    Primary Location:
    US, California, Santa Clara

    Additional Locations:
    US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin

    Business group:

    Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs.

    With the first "Open System Foundry" model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient and sustainable source of supply.


    Posting Statement:

    All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

    Position of Trust N/A

    Benefits:
    We

    offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.

    Find more information about all of our Amazing Benefits here:

    Annual Salary Range for jobs which could be performed in

    US, California:
    $118,860.00-$196,720.00

    S

    al

    ary

    range

    dependent on a number of factors including location and experience.

    Work Model for this Role

    This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

    In certain circumstances the work model may change to accommodate business needs.
    #J-18808-Ljbffr
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