- Manage an ASIC design verification team responsible for various processing blocks in a SOC. Drive verification planning and execution, innovative verification methodology development, functional and code coverage closure. Participate in silicon architecture, micro-architecture development, interface with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams
- Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, capacity planners and supply chain experts
- Contribute to and drive development of and maintain overall silicon strategy aligned to corporation's Long Range Plan objectives
- Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection and IP licensing
- Identify candidates, hire, schedule, support and train a team of ASIC engineers in order to develop products on time and on budget
- Contribute to, analyze, review SOWs from vendors, supporting documentation, requirements sets that meet the needs of internal customers
- Support engineering teams to define, debug, implement and deliver total solutions around purpose built ASICs
- Define, implement and maintain key performance indicators (KPI) for areas of responsibility
- Partner with technical program management and supply chain team members to manage external development partners, suppliers and vendors
- B.S. or M.S. degree in Computer Engineering or Electrical Engineering, relevant technical field, or equivalent practical experience
- 10+ years experience managing ASIC/SoC design verification teams at the Director or Manager level
- Clear understanding of complexities involved with various design verification tools, including Synopsys VCS or Cadence Xcelium Simulator, Verdi, JasperGold or VC Formal
- Track record of first-pass success in ASIC Development
- Experience working across multiple projects and adjusting priorities in partnership with stakeholders
- Experience managing and delivering UVM constrained random test benches
- Experience with interpreting functional specs and creating comprehensive test plan
- Hands-on experience with complex subsystems like memory/LPDDR/HBM, cache, PCIE or Network on chip and with performance verification
- Knowledge of video coding standards, signal processing algorithms, neural networks and machine learning concepts, and/or other neural network development framework
- Experience in formal verification techniques and methodologies
- Experience with managing and delivering Formal Verification sign-off for complex designs
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Design Verification Engineer
3 days ago
META Sunnyvale, United StatesSummary: · Reality Labs focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta's Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learn ...
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Design Verification Engineer
1 day ago
NR Consulting Sunnyvale, United StatesJob Title: Design Verification Engineer · Duration: 12 mos + Possible extension · Location: : Sunnyvale CA · Description: · •Strong DV background (test plan development, test writing, SystemVerilog, UVM) · Duties:Write and augment existing testplans. · Implement testbench and s ...
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Design Verification Engineer
1 day ago
Baidu Sunnyvale, United StatesDo you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry and have the desire to solve them? Do you want to work with a world-class team to explore the fast-growing AI hardware opportunities and impact on AI industry?W ...
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Design Verification Engineer
1 day ago
QuEST Global Mountain View, United StatesDesign Verification Engineer · San Jose CA · JOB DESCRIPTION · Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc. · ? Strong HVL (UVM or SystemVerilog with OVM), C/C++, Perl, TCL programming skills. ...
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Design Verification Engineer
4 days ago
Quest Global Mountain View, CA, United StatesDesign Verification Engineer · San Jose CA · JOB DESCRIPTION · Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc. · ○ Strong HVL (UVM or SystemVerilog with OVM), C/C++, Perl, TCL programming skills. ...
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ASIC Engineer, Design Verification
4 days ago
Meta Sunnyvale, CA, United StatesMeta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. · As a Design Verification Engineer, you will be part ...
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Design Verification Engineer
1 day ago
Mirafra Technologies Santa Clara, United StatesLooking to add DV Engineers in Irvine, San Diego and Santa Clara. · On going needs additional 10 engineers in team. · Position detail: SOC verification · Experience level : 5-20 years · Architect block and full-chip verification environments using HVLs and constrained random ...
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Design Verification Engineer
4 days ago
Capgemini Engineering Santa Clara, United StatesWe are seeking a Design Verification Engineer with below skills. · Total 10 years of experience in UVM based verification. · System Verilog assertions experience. · Familiarity with C/C++ model integration in verification environments. · Debug skills at IP and subsystem level. · ...
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ASIC Design Verification Engineer
1 day ago
Sql Pager LLC Sunnyvale, United StatesASIC Design Verification Engineer · Client OverviewOur client is building the first latency optimized SoC for their industry. Using its proven AI accelerator designs, we are targeting best in class latency with order of magnitude improvements for years to come. · Low Latency has ...
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Design Verification Engineer
1 week ago
Mirafra Technologies Santa Clara, United StatesLooking to add DV Engineers in Irvine, San Diego and Santa Clara. · Make sure to apply quickly in order to maximise your chances of being considered for an interview Read the complete job description below. · On going needs additional 10 engineers in team. · Position detail: S ...
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Design Verification Engineers
1 day ago
Tachyum Santa Clara, United StatesWe are looking for talented Verification Engineers to expand our International Design Verification team. · Qualifications · Bachelor's or Master's in Electrical or Computer Science · 4 years of Design Verification experience · Very good understanding of Design Verification go ...
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Senior Design Verification Engineer
1 day ago
Intuitive Sunnyvale, United StatesCompany Description · At Intuitive, we are united behind our mission: we believe that minimally invasive care is life-enhancing care. Through ingenuity and intelligent technology, we expand the potential of physicians to heal without constraints. · As a pioneer and market leade ...
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Design Verification Engineer
1 week ago
Intel Santa Clara, United States**Job Description** · **Do Something Wonderful** · Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea ...
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Design Verification Engineer
1 day ago
Capgemini Engineering Santa Clara, United StatesWe are seeking a Design Verification Engineer with below skills. · Total 10 years of experience in UVM based verification. · System Verilog assertions experience. · Familiarity with C/C++ model integration in verification environments. · Debug skills at IP and subsystem level ...
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Senior Design Verification Engineer
3 weeks ago
Intuitive Surgical Sunnyvale, United States OTHERJob Description · Primary Function of Position: · Verification of FPGA's on daVinci systems for RTL functional correctness · Roles & Responsibilities: · Starting from testplanning to closing verification using coverage metrics · Testbench development from scratch and modifying e ...
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Senior Design Verification Engineer
1 week ago
Acceler8 Talent Mountain View, United StatesSenior Design Verification Engineer · Acceler8 Talent is seeking a Senior Design Verification Engineer to join an early stage AI hardware startup that's building custom chips for LLMs, achieving substantially greater efficiency and performance compared to current market leading p ...
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CPU Design Verification Engineer
1 day ago
Prodapt ASIC services (Formerly Innovative Logic) Mountain View, United StatesProdapt ASIC services (formerly Innovative Logic) is the leading provider of SoC ASIC/FPGA and Embedded Software services. Our business model is to offer our services based on turnkey, Offshore design center (ODC) or staff augmentation. · We're seeking a CPU Design Verification ...
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Principal Design Verification Engineer
1 week ago
Microsoft Corporation Mountain View, United StatesThe Artificial Intelligence Silicon Engineering team is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge AI designs that can perform c ...
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Senior Design Verification Engineer
6 days ago
Understanding Recruitment Mountain View, United StatesSenior Design Verification Engineer · Acceler8 Talent is seeking a Senior Design Verification Engineer to join an early stage AI hardware startup that's building custom chips for LLMs, achieving substantially greater efficiency and performance compared to current market leading p ...
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Senior Design Verification Engineer
1 day ago
Oho Group Ltd Mountain View, United StatesA $100m+ VC backed RISC-V scale up are looking for multiple Verification Engineers as they continue to accelerate their growth this year · They are at 400 people worldwide so have already been able to circumnavigate a lot of the typical speedbumps that effect early stage compani ...
ASIC Engineering Manager, Design Verification - Sunnyvale, United States - META
Description
The ideal candidate will be a consensus-driven leader with management and leadership experience in small to large size organizations, with comprehensive system and silicon development experience, and a proven track record of first-pass success in ASIC and Systems.
ASIC Engineering Manager, Design Verification Responsibilities
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