Sta engineer jobs in United States

This is a full-time, on-site role for Senior Physical Design Engineer/STA located in California, · This Senior Physical Design Engineer will be responsible for end-to-end implementation of physical design processes, · ,timing closure,power optimization,and collaborating with cros ...

In this position ... Manage quality of products supplied to Ford Service from multiple supplier sites, both service unique and production common for assigned suppliers. At Ford Motor Company, we believe freedom of movement drives human progress. · ...

Lead Critical Supplier Process to drive Supplier Quality Reject (QR) performance improvement. · ...

In this position you will manage the quality of products supplied to Ford Service from multiple sites and maintain the STA 6-Panel and metrics. · ...

We are searching for a hardworking engineer to join our exciting team of problem solvers. · Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. ...

We are searching for a hardworking engineer to join our exciting team of problem solvers. As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC Timing: Full chip and block level timing closure/constraints ownership throughout the entire project. ...

· Company Description · Insilico is an End-to-End specialized VLSI, Embedded Design & Software services and solutions company. It operates in the "Compute" & "Connectivity" space. · Insilico is founded by industry veterans, who are strong leaders and practitioners with diverse e ...

Saika Technologies looking for DFT Engineer with more than · 6 years of experience. · Perform full‑chip and block‑level static timing analysis · for advanced ASIC designs. · ...

This is a full-time role for a Senior Physical Design Engineer/STA located in California. · Perform full-chip and block-level static timing analysis for advanced ASIC designs. · ...

We are searching for a hardworking engineer to join our exciting team of problem solvers. · Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. · As an ASIC STA Engineer, you will have responsibilities spanning various a ...

+Member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. · ++Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block lev ...

In this position... · Lead Critical Supplier Process to drive Supplier Quality Reject (QR) performance improvement. · Participate in Whiteboard reviews and assigned sub-system PRT (Powertrain Variability Reduction Team) meetings. Drive resolution of external supplier process -1MI ...

We are looking for an STA Engineer to work with our AI team. The position requires expertise in timing checks using the Siemens Fractal/Crosscheck tool. · ...

Job Description: · ◦ Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction. · ◦ Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and powe ...

We are looking for a STA Engineer to join our team. The successful candidate will be responsible for quality checks of incoming IPs and configuring the crosscheck tool to filter out real violations and flag QA issues. · Timing expert preferably w/ Siemens Fractal/Crosscheck tool ...

Support QR procedures by reviewing threshold QRs and providing support for QR Dispute resolution. · ...

Job Description: · ◦ Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction. · ◦ Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and powe ...

We are searching for a hardworking engineer to join our exciting team of problem solvers. · Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execut ...

Heads up that I am going to be opening additional STA contractor reqs. · The STA requirements will be the same as the previous one with following specifics, · Subsystem‑level and full‑chip timing closure experience is required General familiarity with 2nm/3nm signoff criteria is ...

The job involves overseeing fullchip SDCs and working with physical design and DFT teams to close fullchip timing in multiple timing modes. · Member of design team who oversees fullchip SDCs. · ...