- Participate in MLA architecture, micro-architecture and feature discussions and reviews
- Define and develop MLA test bench components using UVM & SystemVerilog
- Develop DV reference models as needed in C or SystemVerilog
- Develop and execute a test plan
- Verification execution of MLA and MLSoC functionality and performance measurements
- Manage debug test and regression failures, as well emulation failures
- BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 8+ years of experience in functional verification of pipe-line based design preferably MLAs, DSPs, CPUs or GPUs
- Very good experience of UVM and SystemVerilog based verification methodology is a must
- Proficiency in C/C++ programming is a plus
- Working experience on emulation is a plus
- Good debug and problem solving skill
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Sr. Staff Engineer - San Jose, CA, United States - SiMa Technologies
Description
Description Job Title: Sr. Staff Engineer - Machine Learning (MLA) Verification Job Location: San Jose, CAJob ID: AI2309
Job Description: The MLA Design Verification (DV) team at SiMa is involved in the functional verification of Machine Learning Accelerator (MLA) and computer vision pipeline at block, sub-system and SoC level. Will also be involved in bringup and debug on emulator. Responsibilities: As the MLA Design Verification Engineer, you will
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