- Stitching multiple scan chains across different IP(mixed signal) and clock domains.
- Scan vectors generation, and verification at different stages of the design.
- Validating scan coverage across design.
- Provide SoC (top) level constraints and partitions for RTL/Logic designers, floorplan & PD engineers, DFT requirements
- Perform top/block-level DFT insertion including scan compression, boundary scan, JTAG, IEEE 1500 wrapper, MBIST, LBIST, ATPG and pattern simulation.
- Verify DFT circuitry and interface with other blocks, debug timing simulation issues.
- Closely work with physical design team to generate and validate timing constraints.
- Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning.
- Be able to work independently and own the complete task from DFT specification to final pattern delivery for sub-system and/or SOC.
- Working closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power and area goals, functional and diagnostics test coverage
- Ability to lead/manage a team, with active technical interaction with engineering teams
- Education: BSEE, in Electrical/Computer) OR (MSEE, in (Electrical/Computer)
- 10+ years of hands-on experience with DFT and test flow with commercial EDA tools (Synopsys, Mentor) for large and complex SoCs.
- Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST, LBIST. Experience with Synopsys DFT Compiler, Tetramax and VCS is required.
- Experience with TestMaxDFT, SMS, TestMax Advisor tool suite is a plus.
- Experience in RTL simulation, synthesis, Linting, CDC checks, STA, DFT, quality metrics
- Hands-on expertise in writing System Verilog and VHDL
- Hands-on in Perl/TCL/Python/Unix scripting
- Excellent analytical, and problem-solving skills
- 8+ years' industry experience, Master's degree or equivalent in EE or Computer Engineering (CE)
- Experience with JTAG interface.
- Experience with TAP controller architecture
- Experience with Cadence tools for DFT
- Experience with at speed vectors, Boundary scan, Compression mode etc.
-
DFT Engineer
6 days ago
Intelliswift Software San Jose, United StatesMust Have skills: · Strong DFT background (such as Analog DFT, MBIST, IEEE1687 and others) · Tessent MBIST insertion, tessent MBIST pattern generation and simulation using Tessent flow. · Memory BIST insertion and verification experience (SRAM, CAM, eDRAM) · Detailed Job Descript ...
-
DFT Engineer
2 days ago
ACL Digital San Jose, United StatesPosition: DFT Engineer · Location: San Jose, CA / Austin, TX · Required Skills: · 5+ years of experience of working in DFT. · Running MBIST simulations, including gate-level with timing corners and debugging. · Assist MBIST/DFT leads and Interact with RTL counterparts to resolve ...
-
DFT Engineer
1 week ago
ACL Digital San Jose, United StatesPosition: DFT Engineer · Location: San Jose, CA · Required Skills: · 5+ years of experience of working in DFT. · Understanding basics of DFT structures, MBIST, Boundary Scan Tap Controller · Hands on experience with industry standard ATPG tools, MBIST, simulation and debugging. · ...
-
DFT Engineer
3 weeks ago
ATR International Milpitas, United StatesJob Description: · Our Client is seeking a DFT Engineer for the R&D team based out of our Milpitas, CA Office This position is a hands-on technical position, working closely with the customer, design, and implementation teams Primary Responsibilities: · Support and work closely ...
-
DFT Engineer Intern
2 days ago
Ambarella Santa Clara, United States Full timePosition Responsibilities: · Logic Design to support DFT features · Automate DFT Flows (Scan, Compression & MBIST) used for complex multi-million gate SoC · Verification of DFT Logic and analysis of fault coverage · Timing analysis for DFT Modes · Minimum Requirements: · MSEE in ...
-
DFT Engineer
3 weeks ago
Ampcus Incorporated Santa Clara, United StatesRole : DFT Engineer · Location: Santa Clara (US:95054), CA · Qualification/Experience/Skills Required · • 10+ years of hands-on experience with DFT and test flow with commercial EDA tools (Synopsys, Mentor) for large and complex SoCs. · • Strong fundamental knowledge of DFT techn ...
-
Senior DFT Engineer
1 week ago
NVIDIA Santa Clara, United StatesNVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of ...
-
DFT Engineer
2 days ago
ATR International Milpitas, United StatesJob Description · Job DescriptionThis position is a hands-on technical position, working closely with the customer, design, and implementation teams. · Primary Responsibilities: · Support and work closely with automotive customers (with special emphasis on in-system test using LB ...
-
Senior DFT Engineer
3 days ago
Chelsea Search Group San Jose, United StatesSenior DFT Engineer · Remote/work from any US location · Full-time/Direct-hire + Benefits · US Citizen or US Permanent Resident only · Job Description: · • Lead efforts to map customer designs into company's ASIC technology · • Timing constraints · • Simulation, Conduct Code Synt ...
-
Sr. DFT Engineer
2 weeks ago
Ambarella Santa Clara, United StatesAmbarella, a worldwide leader in edge AI semiconductors and software, is on a mission to bring artificial intelligence to all types of everyday devices, for enhanced environmental perception in everything from security cameras to robots to autonomous vehicles. · Position Responsi ...
-
Sr. DFT Engineer
6 days ago
Ambarella Santa Clara, United StatesJob Description · Ambarella, a worldwide leader in edge AI semiconductors and software, is on a mission to bring artificial intelligence to all types of everyday devices, for enhanced environmental perception in everything from security cameras to robots to autonomous vehicles. ...
-
DFT Engineer
1 week ago
NVIDIA Santa Clara, United States Full timeNVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of ...
-
DFT Engineer
6 days ago
Enfabrica Mountain View, United StatesSummary · Join an ambitious, experienced team of silicon and distributed systems experts as a Design For Test engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed c ...
-
SoC DFT Engineer
1 week ago
Apple Cupertino, United StatesSoC DFT Engineer · Santa Clara Valley (Cupertino),California,United States · Hardware · Do you love crafting sophisticated solutions to highly sophisticated challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help ...
-
DFT Engineer
1 month ago
QData Santa Clara, United States contract5-10 years of hands on experience with different DFX architectures. Good to have exposure to multi-core and multi-processor architectures Has participated in multiple SoC DFX verification till tapeout stage Experience writing SoC testplans and re-using existing SoC verification i ...
-
SoC DFT Engineer
1 week ago
Apple Cupertino, United StatesSoC DFT Engineer · Santa Clara Valley (Cupertino),California,United States · Hardware · Do you love crafting sophisticated solutions to highly sophisticated challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, youll he ...
-
DFT Verification Engineer
4 weeks ago
Ursus Inc Santa Clara, United StatesJOB TITLE: DFT Verification Engineer · **TOP 3 SKILLS:** DFT/Mbist, Scan Insertion, Design Verification · LOCATION: Santa Clara, CA or Austin, TX · DURATION: Direct · RATE RANGE: $160,000 - $200,000 · SUMMARY: · Rivos supports the intense requirements of the large language mode ...
-
SoC DFT Engineer
6 days ago
Apple Cupertino, United StatesSummary · Posted: May 10, 2023 · Role Number: · Do you love crafting sophisticated solutions to highly sophisticated challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-gen ...
-
SoC DFT Engineer
5 days ago
Apple Cupertino, United StatesSoC DFT Engineer · Santa Clara Valley (Cupertino),California,United States · Hardware · Do you love crafting sophisticated solutions to highly sophisticated challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help ...
-
DFT Engineer Intern
1 week ago
Ambarella Santa Clara, United StatesJob Description · Position Responsibilities: Logic Design to support DFT features · Automate DFT Flows (Scan, Compression & MBIST) used for complex multi-million gate SoC · Verification of DFT Logic and analysis of fault coverage · Timing analysis for DFT Modes · Minimum Requir ...
DFT Engineer - Santa Clara, United States - Talent Software Services
Description
DFT EngineerJob Summary: Talent Software Services is in search of a DFT Engineer for a contract position in Santa Clara, CA. The opportunity will be eight months with a strong chance for a long-term extension.
Primary Responsibilities/Accountabilities:
Providing consulting opportunities to TALENTed people since 1987, we offer a host of opportunities including contract, contract to hire and permanent placement. Let's talk
