DFT Engineer Intern - Santa Clara, United States - Ambarella

Description

• Logic Design to support DFT features
• Automate DFT Flows (Scan, Compression & MBIST) used for complex multi-million gate SoC
• Verification of DFT Logic and analysis of fault coverage
• Timing analysis for DFT Modes

• MSEE in Electrical / Computer Engineering
• Knowledge of DFT fundamentals
• Knowledge of Logic design & Static timing analysis
• Knowledge of Verilog and any scripting language