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    Senior Principal RTL Design Engineer - San Jose, United States - Rambus

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    Description

    Overview:

    Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Senior Principal Digital RTL Design Engineer to join our Memory Interface Chip team in San Jose. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

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    As a Senior Principal Engineer, the candidate will be reporting to the VP of Engineering and is a Full Time position. The candidate will be part of a design team for the new high performance DDR5 family of products such as Power Management IC (PMIC), SPD Hub(s), Temperature Sensor (TS) as well as other new memory technologies to help grow the business for the Memory Interface Chip Business Unit.

    Responsibilities:
    • Digital design lead for DDR5 PMICs, Hub(s) and TS
    • RTL code and verification methodology
    • Develop the IP
    • Full chip integration
    • Verilog modeling
    • Guide verification team for the code coverage
    • Develop the next generation of products.
    Qualifications:
    • Bachelors or masters Degree with 7+ years of professional experience
    • Strong background in Digital RTL design experience
    • Familiarity with industry standard interface protocol such as I3C, I2C, SMBus
    • Familiarity with DDR5 DRAM, DIMM topology and overall, DIMM operation
    • Ability to document design techniques, test, and verification methodology.
    • Python/perl script development
    • Interface with debug, test, product, and reliability engineers for product qualification
    • Interface with application engineers for customer support

    About Rambus

    With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.

    Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.

    The US salary range for this full-time position is $150,300 to $279,100. Our salary ranges are determined by role, level and location. The successful candidates starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.

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    Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

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    Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application.

    For more information about Rambus, visit For additional information on life at Rambus and our current openings, check

    #LI-BD1

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