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    Hardware System Engineer - Austin, United States - Apple

    Apple
    Apple Austin, United States

    2 weeks ago

    Apple background
    Description
    Summary

    Posted: Mar 21, 2023

    Role Number:

    The iPhone HW Engineering team is seeking an hard-working electrical hardware engineer to work on the iPhone system technologies area - IO interfaces. The ideal candidate should have deep knowledge with all aspects of high speed and low speed interfaces and their implementation on hardware systems, including IO specs/protocol, controller/PHY high level design in silicon, system integration, silicon/system bring up, validation, performance tuning, and issue debug.

    Key Qualifications
    • Strong EE fundamentals and problem solving skills
    • Familiar with SoC and mobile system architecture
    • Knowledge and experience with high speed interfaces such as USB, PCIE, DisplayPort, MIPI, and lower speed interfaces such as SPI, I2C, UART, JTAG, GPIO, etc
    • Experience with using test equipment such as oscilloscope, power supply, and logic analyzers is required
    • Experience with using frequency and time domain tools such as VNA and TDR is highly desired
    • SI/PI analysis experience using spice to run channel simulation is a plus
    • Excellent problem solving, collaboration, and interpersonal skills, ability to work independently, and proven ability to innovate are required
    Description

    Directly work on high speed and low speed IO interfaces architecture and implementation on iPhone systems, and develop strategies and infrastructure for IO bring up, validation and system integration Work closely with x-functional teams, such as platform architecture, mixed signal design, silicon validation, software/firmware, QA, operation and factory CM teams to drive design, development, debug and production. Perform system level analysis by conducting simulation, lab measurement and characterization to identify the efficient IO solution in power and routing space constrained HW systems System schematic and MLB layout review and sign off SOC silicon IO specs review and sign off Up to 10% domestic/international travel may be required

    Education & Experience

    BSEE plus a minimum of 3 years, or MS/PhD plus a minimum of 2 years relevant industrial experience

    Additional Requirements

    Additional Requirements
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