Jobs

    Senior Vice President - California, United States - Faststream Technologies

    Faststream Technologies
    Faststream Technologies California, United States

    3 weeks ago

    Default job background
    Description

    Responsibilities:

    • Lead ASIC/SoC/IP macro design team to develop and productize next generation customer/in-house mixed-signal communication SoCs
    • Work with cross-functional project teams to define product specifications, system architecture, HW/SW partitioning, and execution plan
    • Implement best SoC development practices and improve design methodology to maximize efficiency and predictability
    • Deliver chip architecture, design, integration, programming model, verification, and manage hand-off to backend
    • Validate silicon, support system integration, and production testing
    • Drive innovation and provides leadership to the organization to ensure world-class system solutions and flawless execution
    • Contribute to Architecture and micro-architecture definition
    • Hands-on RTL design development of next generation IoT Embedded devices
    • Create architecture and design specification documents
    • Select, evaluate, and recommend internal and third-party IPs
    • Analyze MCU/SoC/ASIC Performance, power, area, schedule tradeoffs
    • Preform benchmark simulations to assess performance and power
    • Perform gate count analysis to asses area
    • Perform schedule vs features analysis to help optimize schedule
    • Embedded power management architectures, advanced low power techniques, SoC clocking and reset
    • RISC-V and ARM architectures
    • Understanding of modern SoC architectures and PPA (Performance, Power, and Area) tradeoffs, digital design, and ASIC/SoC micro-architecture
    • AI/ML hardware Acceleration for IoT MCU devices
    • Manage team, hire, and retain best talent

    Qualifications:

    • Proven track record of success in high-performance/high-volume semiconductor industry
    • SoC, embedded CPU and bus architectures, networking, and control interfaces
    • Communications / DSP algorithms and power / area efficient implementations
    • Digital IC design, design for low power and high speed, design for test (DFT)
    • System modeling, RTL coding, Lint / CDC checking, simulation, synthesis, power analysis, timing analysis in Cadence / Synopsys design environments
    • Directed and constrained random verification, UVM methodology
    • Embedded systems FPGA emulation, lab debug and chip validation
    • Project planning and execution, and performing design tradeoffs to achieve performance, power, die size, and schedule targets
    • Self-motivated, excellent communication skills, and ability to excel and to provide leadership in a fast-paced environment
    • Senior Management experience preferred
    • B.Tech. / M. Tech. / Phd in Electronics Engineering or related with 20+ years of experience
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