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    Senior Staff Engineer, ASIC Verification Engineering - San Diego, United States - Conductor

    Conductor
    Conductor San Diego, United States

    2 days ago

    Default job background
    Description
    What You'll Do

    The ACD Design verification team independently verifies the ASIC designs against standard specifications. This gives an unbiased view of ASICs as compared to the design engineers.

    This helps the designs to stick to standard specifications and helps in detection of bugs in early stages of the design cycle and saves engineering costs.

    The ACD Design Verification team verifies the ASICs targeted for designs of GNSS Location, Cellular modem RF and High-Speed interface.


    You will get an opportunity to work cutting edge technologies and contribute to the cutting-edge products designed by Samsung for great customer experiences.

    You will get involved in ASIC verification of the designs targeted for the wearables and handsets and you will be designing the test benches at the block level, SoC level and helping in verification closures.


    Location:
    San Diego, CA

    This is a Hybrid role, working onsite at our San Diego office location at least 3 days per week with the flexibility to work remotely the remainder of your time

    Job ID: 42028

    Collaborate with RTL Designers, System Architects to define verification specifications.


    Design the test suites for full chip and block level verification, develop direct and constrained random testcases, analyze and debug simulations at RTL and Gate level.

    Build the functional coverage models, collect and analyze coverage data.

    Build test benches for Low Power designs, analyze simulations with Hybrid UPF and PG netlists.

    Manage regression analysis, file and track bugs using bug tracking systems.

    What You Bring


    Bachelors with 15+ years of relevant industry experience, or Masters with 13+ years or PhD with 10+ years in Electrical Engineering or related field preferred.

    Experience in understanding the design needs and specifications, developing and executing test plans

    Experience in developing test benches using SystemVerilog UVM, testcase development skills for constrained random and directed scenarios

    Excellent simulation debugging and problem-solving skills

    Ability to adopt new methodologies and techniques, promote them across the organization

    Experience and knowledge of EDA tools: Simulator (Synopsys VCS or Cadence Xcelium or Siemens Questasim or equivalent tools), debugging tools (Synopsys Verdi or Cadence Simvision)

    Fluency in Hardware Verification Languages like SystemVerilog, e-Language or Vera. Excellent methodology skills in UVM/OVM is preferred.

    Experience with DSP and SoC verification would be preferred

    You're inclusive, adapting your style to the situation and diverse global norms of our people.

    An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.

    You're collaborative, building relationships, humbly offering support and openly welcoming approaches.

    Innovative and creative, you proactively explore new ideas and adapt quickly to change.

    #LI-MS1

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