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    Design Verification Engineer - San Diego, CA, United States - Verilab

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    Description
    You will be exposed to a diverse range of designs and application areas. We work on leading edge Audio, Automotive, Comms, Processors, Space, Video and more.

    You will have the opportunity to travel, present at conferences, win Best Paper awards, or get involved with industry standards.

    As a permanent full-time employee of Verilab, you will be responsible for all aspects of verification planning, management and implementation.

    You will be directly involved with helping build and grow client relationships.
    BSc/MSc in Electronic Engineering, Computer Engineering, or Computer Science.
    ~7 years of project-proven verification experience.
    ~ Complex transaction-based checkers (e.g. scoreboards with data translation and ordering)
    ~ Register models


    Verification planning:
    Ownership of work, from planning to implementation.
    C/C++ developing, or integrating, reference models into SystemVerilog/UVM environments.
    Experience leading a technical team, including mentoring, training, and performing technical peer reviews.
    Python or Perl.
    Verilab is an established international professional services firm of verification experts. Founded in 2000, we specialize in solving the toughest functional verification problems for ASIC, FPGA and independent IP development. Our work ranges from rescuing projects struggling with verification, through sophisticated verification IP development, to complete methodology engineering. Full-time permanent employee with competitive salary.
    ~20 days paid vacation and observed holidays.
    ~Medical, dental, vision, term life, AD&D, and disability (100% of all premiums covered by Verilab).
    ~ Leading industry career and personal development training.

    The ability to travel is required.


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