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    Design Verification Engineer - San Diego, United States - OPENEDGES Technology, Inc.

    OPENEDGES Technology, Inc.
    OPENEDGES Technology, Inc. San Diego, United States

    3 weeks ago

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    Description

    OPENEDGES develops AI Edge Computing semiconductor IPs, so that more people can enjoy AI technology closer.

    Have you got what it takes to succeed The following information should be read carefully by all candidates.

    ???? Location: San Jose, CA, USA or Austin, TX, USA

    ???? Position: Design Verification Engineer

    OPENEDGES is the world's only total memory system and AI platform IP solution company that has delivered NPU, memory controllers, DDR PHY, and on-chip interconnect IPs all together in one place since 2017.

    Job Summary:

    OPENEDGES is seeking highly motivated, qualified individuals to join the Design Verification (DV) team for our upcoming configurable cache coherent Network-on-Chip (NoC) program. This exciting position based in San Jose, CA, or Austin TX, offers opportunities to work within a veteran team of industry experts to solve state of the art DV challenges as they apply to the complexities of a coherent mesh fabric. Currently we are staffing the team for several levels and are interested in folks who are attracted to working in entrepreneurial environments with small to mid-size teams. We are looking for team players with alignment for these types of products with aggressive schedules, have hands-on experience in all aspects of DV efforts, and can bring to bear their expertise in making our effort a success.

    Roles & Responsibilities:

    The successful Design Verification Engineer (DVE) will be responsible for:

    • Collaborating with architecture/design teams to understand the NoC design
    • Apply state of the art methods to author comprehensive DV plans/schedules/tracking
    • Establish and/or contribute to required DV flows/methodologies
    • Work with vendors to integrate UVM-based verification IP into a complete testbench solution
    • Determine and implement required UVM-based correctness checking
    • Creating a UVM-based constrained random stimulus suite to achieve high coverage
    • Implement UVM-based tracking methods to acquire and track coverage to closure
    • Hands-on debugging simulation fails down to root-cause (Verilog RTL)
    • Demonstrating good communication skills, works well in small dynamic teams

    Required Qualifications:

    The ideal DVE candidate will have a reasonable mix of the following credentials:

    • MSEE/MSCE +5 years, BSEE/BSCE years of relevant experience/track record
    • Knowledge/experience in the following areas: 1) Cache coherent memory architectures and NoC designs, 2) AMBA buses: CHI, CSL, AXI(n), ACE, APB, 3) Standard IP: DDR(x), PCI, PCIe, ARM, X86, RISC-V
    • Hands-on development of testbenches using Verilog, SV/UVM, RAL, SVA, ABV, UPF, XProp
    • Experience in installing/configuring vendor IP for highly integrated testbench design
    • Experience using industry standard toolsets
    • Scripting languages: PERL/Python/Tcl/XML

    Preferred Qualifications:

    • Formal verification methods, emulation experience

    Benefits:

    • Medical, dental, and vision benefits
    • Life insurance
    • 401k retirement plan
    • Paid time off, paid holidays, sick leave, etc.
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