- Demonstrated capability working in a high performing team culture which includes excellent teamwork and leadership skills, demonstrated problem solving and prioritization skills.
- Excellent written and oral communication skills.
- Capable of presenting information clearly and effectively to multiple audiences with varying degrees of technical background.
- Capable of working autonomously with minimal oversight or coaching.
- Demonstrated leadership experience in factory level projects and executing projects in a timely manner.
- Project management skills to execute roadmaps that drive defect/yield/efficiency/cost improvements based on both known impact and program risk factors.
- Capable of being both collaborative and critical.
- Must have a Bachelor's or a Masters degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, Material Science, Microelectronics Engineering, Chemistry, Physics or related field.
- 3+ years previous experience in the semiconductor industry.
- This position is not eligible for Intel immigration sponsorship.
- 5+ years experience in the semiconductor industry.
- 3+ years experience in process integration or defect reduction for backend interconnect or advanced packaging processes
- 3+ years experience with design of experiments (DOE) principles.
- 3+ years experience in data analysis and statistical process control (JMP, SQL, PCS).
- Strong understanding of semiconductor process flow and advanced packaging.
- Understands concepts of process capability, true spec, and variance.
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NM Experienced Process Integration and Defect Reduction Yield Engineer - ALGODONES, United States - INTEL Careers
Description
Job Description
The New Mexico Disaggregation Manufacturing Organization (NM DMO) Yield Department is looking for process integration and defect reduction engineers to support interconnect and advanced packaging semiconductor chip fabrication. Engineers in the NM DMO Yield Department will support Fab 11X and Fab 9 for roles in Foveros, EMIB, Die Prep, Sort, Wafer Level Assembly, and Advanced Packaging. You will partner with all areas of the Yield Department including integration, defect reduction, quality and reliability, device analysis, and yield analysis. Process integration and defect reduction engineers are responsible for sustaining semiconductor fabrication process health on products moving from development to high volume manufacturing while designing and implementing improvements for yield, cost, and defects.
The NM DMO Yield team seeks engineers who enjoy problem solving, data analysis, and leading and participating in cross organizational teams. In this role you will plan and conduct experiments and data analysis to optimize and characterize new fabrication processes and understand sources of variation within the fab. You will be responsible for controlling technology change introduction, monitoring inline defect and parametric performance and end of line yields, finding root cause for processing excursions and navigating fixes. In addition, yield engineers will receive new products from Technology Development (TD) and ensure they are capable of high-volume manufacturing while also driving improvement to quality, reliability, cost, yield, productivity and manufacturability.
The ideal candidate should exhibit the following behavioral traits:
Full time onsite is required during training (estimated 6 months). After training, hybrid "work from home" to be defined by manager and employee, but continued onsite will be required. Role is not eligible for full time remote work.
Relocation assistance provided.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Preferred Qualifications:
