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    Physical Design Engineer Engineering - New York, United States - NauWork

    NauWork
    NauWork New York, United States

    1 week ago

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    Physical Design Engineer

    Engineering - Electrical (Semiconductor)


    Job Description
    A NauWork client is seeking a Physical Design Engineer to join its Mountain View, California team.

    If you are a talented, motivated engineer with experience designing and verifying megascale networking and computing devices, and are looking to grow in a fast-paced, dynamic startup environment this is a position to consider.

    The right candidate is an experienced physical design engineer who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, initial floor plan exploration (in conjunction with microarchitecture definition), through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout.


    Roles and Responsibilities:
    Evaluate, select, and install the CAD tool flow for physical implementation in a cloud-first development environment.

    Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders.


    Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and the interconnect topologies.


    Establish the P+R workflow at the block and chip levels, working with large and complex designs in the latest process technology nodes, at leading edge scale and performance.


    Execute on block-level and top-level physical implementation, from floorplan and power plan, through P+R, through timing closure, LVS/DRC/ERC/ANT checks, and tapeout.

    Interface with package vendors on package type, material, substrate design, escape routing, PI and SI analysis.

    Work with the latest CAD tools to translate static and dynamic analysis of PI and SI into effective silicon solutions.


    Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff.


    Skills/Qualifications:


    Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes.

    Deep experience with the latest CAD tools, e.g., Cadence Innovus, Synopsys ICC, Tempus, PrimeTime SI, PrimeTime PX, StarRC, Calbre.

    Strong familiarity with various analysis tools such as Ansys Redhawk, HFSS, HSPICE.

    Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages.

    Minimum BSEE/CE + 15 years or MSEE/CE + 10 years experience.

    Proven track record of execution on products which have shipped in high-volume.


    Questions:
    Main: 833-NAU-WORK


    • Email:
    • Web:
    • Jobs:Category: Engineering - Electrical (Semiconductor)
    *Position: Physical Design Engineer**Location: Mountain View, California**Job Type: Direct-Hire, Full-Time

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