Sr. Systems Engineer, PHY Standards - San Jose, CA

· Core Responsibilities: · As a DDR Applications Engineer you will be involved with customer interfacing on all phases of phy and controller design of high performance ddr interface from RFQ, RTL to delivery of our final GDSII. Your responsibilities include but are not limited t ...

We are seeking a highly skilled engineer with deep expertise in MIPI protocol validation, SoC bring-up, and Linux kernel driver development. · Perform deep-dive validation of MIPI D‑PHY, C‑PHY, DSI‑2, and CSI‑2 protocols. · Lead initial power‑on, bootloader bring-up, and low‑leve ...

We are seeking a highly skilled engineer with deep expertise in MIPI protocol validation, SoC bring-up, and Linux kernel driver development. · Perform deep-dive validation of MIPI D-PHY, C-PHY, DSI-2, and CSI-2 protocols. · Lead initial power-on, bootloader bring-up, and low-leve ...

We hire and develop leaders and innovators who want to make an impact on the world of technology. · ...

+The Cadence IP team develops industry‑leading IP that powers products across markets—from endpoints to the edge to the cloud. · +We are expanding our SerDes Applications team and are looking for smart engineers who can apply high-speed interface standards such as PCIe,CXL,Ethern ...

The Lead Applications Engineer will use their knowledge of different memory interface standards to architect memory solutions for customers using Cadence DDR IP. · Technical presales of Memory IP · Present Cadence's IP portfolio and capabilities to prospective customers · ...

We hire and develop leaders and innovators who want to make an impact on the world of technology Senior Applications Engineer – DDR Design IP Job DescriptionThe Cadence IP team develops industry leading IPs that enable customers in a variety of markets - from the endpoint to the ...

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology. · The Cadence IP team develops industry leading IPs that enable customers in a variety of markets from the endpoint to the edge to the cloud. · We are growing our Silicon ...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. · Senior Applications Engineer – DDR Design IP · Job Location: San Jose, CA · Job Description · The Cadence IP team develops industry leading IPs that enable customers in ...

· Company Description · Mirafra is a global product engineering services company with expertise in semiconductor design, embedded and application software. · Job Description · Title : Software Test ­ Engineer · Type : Full Time with Mirafra Inc · Location : San Jose, CA · The S ...

We are seeking a highly motivated Field Application Engineer to join our FAE team in San Jose. · Provide technical leadership to sales team covering networking architecture. · Offer design support through schematic and PCB reviews. · Troubleshoot complex issues in the lab using t ...

We are seeking a highly motivated, experienced engineer to join our FAE team Join us to support deployment of industry-leading networking and high-speed communication technologies, including Ethernet, SerDes, PCIe, CAN and LIN, into next-generation automotive and industrial embed ...

Develop innovative MAC and above protocol features for next generation Wi-Fi, Bluetooth, and other connectivity technologies. · Propose protocol mechanisms at international standards organizations (e.g., IEEE 802.11, Wi-Fi Alliance, Bluetooth SIG) · ...

Job Details: · Job Description: · About Altera · Altera is a leading innovator in FPGA technology, delivering programmable solutions that power the world's data-centric applications—from cloud and communications infrastructure to automotive, industrial, and edge AI. Our mission i ...

MaxLinear is seeking a Director of Connectivity to join our team. We are looking for a technical marketing professional focused on wired connectivity technologies. · ...

The Candidate will be an expert with 32Gbps SERDES (Serializer/Deserializaer) based protocols, and must possess recent work experience with PCIe Rev.3, 4 and 5 protocol · Minimum Qualifications: · 1. BSEE / BSCS with 10+ years of experience. · 2. Knowledge of FPGA architectures i ...

· Responsibilities · MaxLinear is seeking a Director of Connectivity to join our team. We are looking for a technical marketing professional focused on wired connectivity technologies, including Ethernet Switches, Ethernet PHYs, MoCA, and G.hn. This role centers on creating clea ...

This is a highly visible technical leadership role requiring deep expertise in DDR and high-speed IO standards, silicon architecture, and cross-functional collaboration from early concept through production. · ...

Cadence seeks a Product Marketing Manager to lead go-to-market initiatives for scale-up and scale-out controller IP solutions. The role involves shaping product positioning, driving customer engagement, and translating technical innovation into compelling marketing narratives. · ...

Position Summary · Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we ...