Senior Applications Engineer – DDR Design IP - San Jose

We hire and develop leaders and innovators who want to make an impact on the world of technology Senior Applications Engineer – DDR Design IP Job DescriptionThe Cadence IP team develops industry leading IPs that enable customers in a variety of markets - from the endpoint to the ...

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology. · The Cadence IP team develops industry leading IPs that enable customers in a variety of markets from the endpoint to the edge to the cloud. · We are growing our Silicon ...

Company: · Qualcomm Technologies, Inc. · Job Area: · Engineering Group, Engineering Group > ASICS Engineering · General Summary: · QCT mixed-signal IP design team is looking for skilled system architect to help design high-speed, high-performance and low-power LPDDR and D2D PHYs ...

· Core Responsibilities: · As a DDR Applications Engineer you will be involved with customer interfacing on all phases of phy and controller design of high performance ddr interface from RFQ, RTL to delivery of our final GDSII. Your responsibilities include but are not limited t ...

Job Title: · Product Definer / System Engineer (DDR/SSD/PMIC) · Position Type: · Full-time · Location: · Santa Clara, CA | Work on-site required · Salary Range / Rate: · Base $160,000-$220,000 + Bonus & Stock Options · Job ID#: · 159363 · Responsibilities · • Define and drive nex ...

Dice is the leading career destination for tech experts at every stage of their careers. · All SI tasks described above (channel modeling, extractions, eye analysis). · Perform power integrity extractions and simulations for high-speed interfaces. · ...

No H1B assistance at this time: · We are seeking a Design Verification Engineer for our Fortune 500 Client in San Jose. The successful candidate will have expertise in design verification methodologies including System Verilog. · A Bachelor's Degree in Electrical and Electronic E ...

Job Title: Product Definer / System Engineer (DDR/SSD/PMIC) · Position Type: Full-time · Location: Santa Clara, CA | Work on-site required · Salary Range / Rate: Base $160,000-$220,000 + Bonus & Stock Options · Job ID#: #159363 · Responsibilities · • Define and drive next-generat ...

Dice is the leading career destination for tech experts at every stage of their careers. · ...

Broadcoms ASIC Product Division is seeking candidates for HBM DDR SERDES Verification Lead Engineer position at our San Jose California Development Center We are seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team You will play a crucial par ...

Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San Jose Development Center. · ...

As a Package Design Engineer at Advanced Technology Search, you'll play a key role in developing high-performance package designs for industry-leading ASICs. These designs feature complex flip-chip-BGA packages with high-speed SerDes and RF/microwave communications A/D D/A conver ...

We are looking for a talented and motivated Hardware Engineer with a Master's degree to join our dynamic team. · ...

Job ID Date posted 04/03/2026 Location San Jose, California Category Quality · Job Overview · As a Senior TPIP Quality & Reliability Engineer (QRE) you'll be the go-to expert for pre-silicon quality of our high-speed I/O (HSIO) subsystems. You'll initially work on DDR, PCIe, eUSB ...

Cadence is seeking a dynamic strategic Product Marketing Manager to lead go-to-market initiatives for advanced DDR/LPDDR memory controller IP solutions. · Develop execute comprehensive go-to-market strategies for memory controller IP aligned with customer needs market dynamics. · ...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. · Job Duties: · Research, design, and develop computer and network software or specialized utility programs for multinational computational software company. · Analyze us ...

Senior Analog Design Engineer (Power Management) · We are seeking a high-caliber Sr. Analog Design Engineer with a deep specialization in high-performance power delivery. In this role, you will be at the forefront of designing the power ecosystems that fuel the next generation of ...

We are seeking a Hardware Design Engineer with 3–5 years of experience in FPGA and SoC development. · The ideal candidate will have strong expertise in RTL design using Verilog/SystemVerilog and hands-on experience with emulation and prototyping platforms such as HAPS, Zebu, Prot ...

Senior Analog Design Engineer (Power Management) · We are seeking a high-caliber Sr. Analog Design Engineer with a deep specialization in high-performance power delivery. In this role, you will be at the forefront of designing the power ecosystems that fuel the next generation of ...

· .Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Conn ...