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    Senior Principal ASIC Design Engineer - San Jose, United States - BAE Systems USA

    BAE Systems USA
    BAE Systems USA San Jose, United States

    1 week ago

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    Description

    **Job Description**

    You don t see it, but it s there. Our employees work on the world s most advanced electronics from saving emissions in the City of Lights to powering the Mars Rover to protecting the F-35 fighter jet. At Electronic Systems, you ll be among the brightest minds, working on the aerospace and defense industry s most difficult problems. Drawing strength from our differences, we re innovating for the future. And you can, too. Our flexible work environment provides you a chance to change the world without giving up your personal life. We put our customers first exemplified by our missions: We Protect Those Who Protect Us and We Innovate For Those Who Move The World. Sound like a team you want to be a part of? Come build your career with BAE Systems.

    We are seeking a very senior level engineer to:

    + Design and RTL coding of high-speed digital circuits on ASIC/FPGAs from concept to production.

    + Defining detailed test plan and implementing Verilog simulation testcases to verify design functionality.

    + Debug product, test and resolve design issues on hardware platforms

    + Define hardware and firmware interfaces, protocols for circuits.

    + Integration of IP cores Buses, Controllers, PHYs, etc with other logic within ASIC/FPGA

    + Coordinate interoperability of digital modules with embedded software

    + Build verification environment using SV/UVM methodology

    + Build reusable bus functional models, monitors, checkers and scoreboards

    + Solid understanding of verification methodologies, especially UVM(SystemVerilog), including:

    + Test planning

    + Testbench creation

    + Code and Functional coverage

    + Directed and random stimulus generation

    + Assertions

    + Regression triage

    Because this role involves a combination of collaborative/in-person and independent work, it will take the form of a **hybrid work format** , with time split between working onsite and remotely.

    **Required Education, Experience, & Skills**

    + Proficient in Verilog language for ASIC/FPGA design

    + Knowledge of ASIC and FPGA design flows is highly desirable

    + Knowledge simulation and verification methodologies (VCS simulator, UVM)

    + Proficient in ASIC/FPGA timing closure/area optimization techniques

    + Hands on Experience with bring-up of ASIC/FPGA designs

    + Excellent organization and communication skills for interacting between different design groups

    + Proficiency in C/C and scripting languages is a plus.

    **Preferred Education, Experience, & Skills**

    + BS in EE or Computer Science, MS or Doctoral degree preferred

    + 10 years of experience in ASIC/FPGA Development (Verilog, System Verilog, UVM)

    **Pay Information**

    Full-Time Salary Range: $ $243100

    Please note: This range is based on our market pay structures. However, individual salaries are determined by a variety of factors including, but not limited to: business considerations, local market conditions, and internal equity, as well as candidate qualifications, such as skills, education, and experience.

    Employee Benefits: At BAE Systems, we support our employees in all aspects of their life, including their health and financial well-being. Regular employees scheduled to work 20 hours per week are offered: health, dental, and vision insurance; health savings accounts; a 401(k) savings plan; disability coverage; and life and accident insurance. We also have an employee assistance program, a legal plan, and other perks including discounts on things like home, auto, and pet insurance. Our leave programs include paid time off, paid holidays, as well as other types of leave, including paid parental, military, bereavement, and any applicable federal and state sick leave. Employees may participate in the company recognition program to receive monetary or non-monetary recognition awards. Other incentives may be available based on position level and/or job specifics.

    **Senior Principal ASIC Design Engineer (Hybrid)**

    **95186BR**

    EEO Career Site Equal Opportunity Employer. Minorities . females . veterans . individuals with disabilities . sexual orientation . gender identity . gender expression

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