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Physical Design - Austin, United States - Talent Software Services
Description
Physical Design (STA) EngineerJob Summary:
Talent Software Services is in search of a Physical Design (STA) Engineer for a contract position in Austin, TX(Hybrid).
The opportunity will be eight months with a strong chance for a long-term extension.Primary Responsibilities/Accountabilities:
Full chip timing constraints development, full chip Static Timing Analysis and Signoff for a complex, multi-clock, multi-voltage SoC
Working with the Systems and Application team to drive timing closure-friendly SoC architecture and IO interfaces/IO pin.
Streamlining the timing signoff criterions, timing analysis methodologies and flows (critical path spice simulation etc.) and develop/enhance auto ECO generation scripts for timing closure.
Analyze and incorporate advance timing signoff flows (SSTA, LOCV Based STA, IR Drop aware STA) into SoC timing signoff flow.
Enhance existing entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip level and block level.Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level)
Ensure quality adherence during all stages of the project life cycle. Drive thorough analysis of existing processes and recommend and implement the process improvements to ensure 'Zero Defect' chips.
Active participation in post silicon validation, correlation and test activities using in-house test and validation lab.
Encouraging and influencing technological innovations in the team
Actively work as part of team both locally & also with remote and multi-site teams
Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change.
Qualifications:
Self-starter with 2-10 years of experience on SOC/Chip level/IP Timing closure and Signoff of high-speed complex design with multiple clocks and power domains with minimal supervision.
Expertise in protocol of Industry standard IO interfaces (e.g., DDR2, SDR, LPDDR, Flash, SPIs, USBHS, USBFS, JTAG, Display etc...)
Experience in analyzing failure in Functional and Test Gate-level simulations with back annotated data and interacting with Verification and DFT team in this respect.
Expertise in running STA analysis and achieving timing closure on multiple high performance and low power designs.Experience in developing and supporting a fully automated STA scripts/flows.
Good understanding of deep submicron parasitic effects, crosstalk effects, newer statistical timing approaches
System Verilog, Python/TCL, Synopsys/Cadence tools
If this job is a match for your background, we would be honored to receive your application
Providing consulting opportunities to TALENTed people since 1987, we offer a host of opportunities including contract, contract to hire and permanent placement.
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