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    Analog Engineer Internship - Santa Clara, United States - Intel

    Intel
    Intel Santa Clara, United States

    4 weeks ago

    Intel background
    InternshipSHIP
    Description

    Job ID: JR Job Category: Intern/Student Primary Location: Santa Clara, CA US Other Locations: US, California, Folsom Job Type: Intern **Analog Engineer Internship - Power delivery**

    **Job Description**

    We are looking for a highly motivated Analog Design Engineer to join the Circuits Power Delivery Team for Intel's next generation of chipsets/SOC. As part of the team, you will be working with experienced engineers, doing design and simulation.

    Responsibilities of this role include, but are not limited to:

    Design, simulation and characterization of circuits and components for LDOs, PLLs, DLLs, thermals

    Design of testbenches and test plans

    Behavioral Traits:

    Good communication, interpersonal and problem-solving skills

    Highly motivated, skilled at working effectively both independently and as a team

    Collaborative skills to work across the organization to achieve goals and thrive in a team-oriented environment

    Responsibilities may be quite diverse of a nonexempt technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school.

    **Qualifications**

    You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.

    Minimum Qualifications:

    The candidate must be pursuing a Master's or PhD degree in Computer Engineering, Electrical Engineering, Computer Science or related field.

    6+ months of experience in:

    Design of on-die power delivery circuits: voltage regulators, power gates, band gap reference, voltage and current monitors

    Relevant industry experience in analog and custom logic design

    Knowledge in semiconductor device and technology

    Proficiency in UNIX

    Available to join for 9 months internship.

    Preferred Qualifications:

    Experience in:

    Mixed signal design

    Design of other analog circuits: LDOs, BandGap, powergate, PLLs, HSIOs, thermal sensors

    Post-silicon debug experience

    **Inside this Business Group**

    The Design Engineering Group is a worldwide team responsible for the design, development, validation, and manufacturing of IPs and SOCs. Our mission is to deliver leadership products through groundbreaking innovations.

    **Other Locations**

    US, California, Folsom

    **Posting Statement**

    All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

    US Intern JR Santa Clara Design Engineering Group

    **Information Our Partners Collect**

    **Your Choices**

    Always Active These technologies are necessary for the Intel experience to function and cannot be switched off in our systems. The technology is usually only set in response to actions made by the device owner which amount to a request for services, such as setting privacy preferences, logging in, filling in forms, maintaining secure login areas, maintaining state across pages (remembering items in a shopping basket), and server load balancing. The device owner can set their preference to block or alert Intel about these technologies, but some parts of the Intel experience will not work. These technologies do not store any personally identifiable information.

    **Analytics**

    Analytics Inactive These technologies allow Intel to count device visits and traffic sources, so Intel can measure and improve the performance of our experiences. The technology helps Intel to know which experiences are the most and least popular and see how device owners interact with the experience. All information these technologies collect is aggregated. If the device owner does not allow these technologies, then Intel will not know when the device owner visited or how the device owner interacted with our experiences.

    **Functional**

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    **Welcome**

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