- Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation. EDUCATION: Bachelor's or Master's in Computer Engineering
- Perform RTL design of digital components in Verilog/systemverilog.
- Analyze/fix Lint and CDC errors of the components.
- Guarantee quality/timely deliverables meeting projects schedule.
- Help to improve/automate design process.
- Knowledge of RISK-V processor integration Express
- Multi-clock domain designs.
- Design constraints for synthesis and static timing analysis.
- Knowledge of AXI/AMBA protocol
- Knowledge of front-end RTL design tools and methodologies.
- Knowledge of scripting languages like Perl, tcl or cshell
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RTL Design Engineer - Santa Clara, United States - Tekwissen
Description
Job Title: RTL Design Engineer - Senior
Work Location: Santa Clara, CA 95054
Duration: 12 Months
Work Type: Contract
Job Type: Onsite
Pay Rate: $80 /Hourly/W2
Overview:
TekWissen Group is a workforce management provider throughout the USA and many other countries in the world. This Client is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories, graphics processors, motherboard chip sets, and a variety of components used in consumer electronics goods.
JOB Description:
KEY RESPONSIBILITIES:
PREFERRED EXPERIENCE:
TekWissen Group is an equal opportunity employer supporting workforce diversity.