- Provide technical assistance to the architecture team in development of next-generation AI accelerators to enable novel machine learning algorithms.
- Work closely with the algorithms teams to understand and evaluate local and global data movement in different potential architectures.
- Work closely with the system software team to develop compilers and ISA extensions to enable new hardware functional units and features at the software level in an SoC setting.
- Work closely with the IC Design team to evaluate various microarchitectures and digital and mixed-signal design collaterals in synchronous and asynchronous architectures and collaborate on microarchitecture development and specification hand-off architecture specifications to the IC Design team.
- Develop functional and/or performance simulators for architecture evaluation, system design, verification, software prototyping and hardware-software co-optimizations.
- Integrate proprietary accelerators and design macros ARM or RISC-V cores.
- Develop and maintain architectural specification and documentation to be used by architecture, design, verification and software teams.
- MSEE with 10+ years or PhD in Electrical Engineering and/or Computer Engineering with a focus on SoC architecture, ML accelerator design, system and performance modeling, and simulation.
- Familiarity with compute architecture, programming models, compiler optimizations and code generation.
- Familiarity with deep learning models and willingness to learn novel algorithms and translate them into specifications for hardware accelerators.
- Familiarity with algorithmic techniques for on-device learning (online/continuous learning) is a plus.
- Deep understanding of processor microarchitectures such as x86, ARM, and RISC-V.
- Strong understanding of memory subsystem functionality, on-chip and off-chip data movement and associated tradeoffs, logic-memory optimizations and efficient code/date placement techniques.
- Experience with SystemC, Python, C/C++ and the ability to write production-ready, annotated code.
- Familiarity with the integration of novel accelerators and design macros with ARM or RISC-V cores.
- Exhibit a high degree of motivation and independence.
- Strong communication skills, both written and verbal.
- PhD in Electrical Engineering and/or Computer Engineering with focus on near- and in-memory computing architectures for AI acceleration.
- Demonstrated track record of owning architecture of an AI accelerator from conception to tape-out. Demonstration of programmability.
- Medical Insurance with 100% coverage of employee premiums
- Dental and Vision Insurance
- 401k match
- Unlimited vacation + all federal holidays
- Company wide time off: Time between Christmas and New Years, first week of August
- Health & Wellness Perk
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ML Hardware Architect - California, United States - Rain AI
2 weeks ago
Description
About Rain:
At Rain AI, we're creating a future with abundant and scalable artificial intelligence by building the world's most cost and energy efficient hardware for AI. Our ultimate goal is to become the dominant hardware company of the AI era.
Rain AI is currently a Series A stage startup and backed by world leaders in AI. Our seed round was led by Sam Altman (OpenAI). In addition, our current VC partners include Y Combinator, Daniel Gross, Jaan Tallinn, Founders X Fund, Airbus Ventures, Liquid 2 Ventures and Deepwater.
About the role:
Rain AI is looking for a ML Hardware Architect to help define the architecture of Rain's next-generation AI accelerators. Given the increased customer demand and ambitious timelines, we are growing our architecture team and open to candidates at various levels (staff to principal).
You would have a large degree of independence and influence at Rain, with an immense opportunity to directly impact one of the most important topics across AI & semiconductor.
This role will be based in the Bay Area, and will report to our Lead Architect.
Responsibilities:
Qualifications:
Preferred qualifications:
Our Benefits:
The anticipated annual base salary for this position in the United States is $220,000 to $320,000. This range does not include any other compensation components or other benefits that an individual may be eligible for.
